San Jose, CA · On-site
$150 - $350/hr
Role Overview We are seeking a highly capable Formal Verification Engineer to join our core product and research team. In this role, you will work closely with our AI engineering, research, and EDA ...
San Jose, CA · On-site
$150 - $350/hr
Role Overview We are seeking a highly capable Formal Verification Engineer to join our core product and research team. In this role, you will work closely with our AI engineering, research, and EDA ...
San Jose, CA · On-site
$159K/yr
Formal Verification Engineer Location: San Jose, CA - Full Time We are looking for formal verification experts to ensure design correctness using mathematical verification techniques and advanced ...
San Jose, CA · On-site
$159K/yr
Formal Verification Engineer Location: San Jose, CA - Full Time We are looking for formal verification experts to ensure design correctness using mathematical verification techniques and advanced ...
San Jose, CA · On-site
$350K/yr
Role Overview We are seeking a highly capable Formal Verification Engineer to join our core product and research team. In this role, you will work closely with our AI engineering, research, and EDA ...
San Jose, CA · On-site
$350K/yr
Role Overview We are seeking a highly capable Formal Verification Engineer to join our core product and research team. In this role, you will work closely with our AI engineering, research, and EDA ...
$184K - $324K/yr
Description As a formal verification engineer working the complete formal verification for single or multiple design blocks and IP's (CPU, Cellular and Connectivity IP, Audio and Image Processing IP ...
$184K - $324K/yr
Description As a formal verification engineer working the complete formal verification for single or multiple design blocks and IP's (CPU, Cellular and Connectivity IP, Audio and Image Processing IP ...
$150K - $277K/yr
Description As a formal verification engineer working the complete formal verification for single or multiple design blocks and IP's (CPU, Cellular and Connectivity IP, Audio and Image Processing IP ...
$150K - $277K/yr
Description As a formal verification engineer working the complete formal verification for single or multiple design blocks and IP's (CPU, Cellular and Connectivity IP, Audio and Image Processing IP ...
Austin, TX · On-site
$134K/yr
Description As a formal verification engineer working the complete formal verification for single or multiple design blocks and IPs (CPU, Cellular and Connectivity IP, Audio and Image Processing IP ...
Austin, TX · On-site
$134K/yr
Description As a formal verification engineer working the complete formal verification for single or multiple design blocks and IPs (CPU, Cellular and Connectivity IP, Audio and Image Processing IP ...
$115K - $194K/yr
Description As a formal verification engineer working the complete formal verification for single or multiple design blocks and IPs (CPU, Cellular and Connectivity IP, Audio and Image Processing IP ...
$115K - $194K/yr
Description As a formal verification engineer working the complete formal verification for single or multiple design blocks and IPs (CPU, Cellular and Connectivity IP, Audio and Image Processing IP ...
Austin, TX · On-site
$120 - $160/hr
Description As a formal verification engineer working the complete formal verification for single or multiple design blocks and IP's (CPU, Cellular and Connectivity IP, Audio and Image Processing IP ...
Austin, TX · On-site
$120 - $160/hr
Description As a formal verification engineer working the complete formal verification for single or multiple design blocks and IP's (CPU, Cellular and Connectivity IP, Audio and Image Processing IP ...
Austin, TX · On-site
$140 - $190/hr
You will serve as a subject matter expert in formal verification methodologies, mentor junior engineers, and collaborate with RTL designers, simulation-based verification engineers, and architects to ...
Austin, TX · On-site
$140 - $190/hr
You will serve as a subject matter expert in formal verification methodologies, mentor junior engineers, and collaborate with RTL designers, simulation-based verification engineers, and architects to ...
$150K - $277K/yr
Description As a formal verification engineer working the complete formal verification for single or multiple design blocks and IP's (CPU, Cellular and Connectivity IP, Audio and Image Processing IP ...
$150K - $277K/yr
Description As a formal verification engineer working the complete formal verification for single or multiple design blocks and IP's (CPU, Cellular and Connectivity IP, Audio and Image Processing IP ...
Austin, TX · On-site
$126K/yr
You will serve as a subject matter expert in formal verification methodologies, mentor junior engineers, and collaborate with RTL designers, simulation-based verification engineers, and architects to ...
Austin, TX · On-site
$126K/yr
You will serve as a subject matter expert in formal verification methodologies, mentor junior engineers, and collaborate with RTL designers, simulation-based verification engineers, and architects to ...
$184K - $324K/yr
Description As a formal verification engineer working the complete formal verification for single or multiple design blocks and IP's (CPU, Cellular and Connectivity IP, Audio and Image Processing IP ...
$184K - $324K/yr
Description As a formal verification engineer working the complete formal verification for single or multiple design blocks and IP's (CPU, Cellular and Connectivity IP, Audio and Image Processing IP ...
Austin, TX · On-site
$134K/yr
Description As a formal verification engineer working the complete formal verification for single or multiple design blocks and IP's (CPU, Cellular and Connectivity IP, Audio and Image Processing IP ...
Austin, TX · On-site
$134K/yr
Description As a formal verification engineer working the complete formal verification for single or multiple design blocks and IP's (CPU, Cellular and Connectivity IP, Audio and Image Processing IP ...
Austin, TX · On-site
$134K/yr
Description As a formal verification engineer working the complete formal verification for single or multiple design blocks and IP's (CPU, Cellular and Connectivity IP, Audio and Image Processing IP ...
Austin, TX · On-site
$134K/yr
Description As a formal verification engineer working the complete formal verification for single or multiple design blocks and IP's (CPU, Cellular and Connectivity IP, Audio and Image Processing IP ...
Austin, TX · Hybrid
$134K/yr
You will serve as a subject matter expert in formal verification methodologies, mentor junior engineers, and collaborate with RTL designers, simulation-based verification engineers, and architects to ...
Austin, TX · Hybrid
$134K/yr
You will serve as a subject matter expert in formal verification methodologies, mentor junior engineers, and collaborate with RTL designers, simulation-based verification engineers, and architects to ...
Beaverton, OR · On-site
$120 - $150/hr
Description As a formal verification engineer working the complete formal verification for single or multiple design blocks and IP's (CPU, Cellular and Connectivity IP, Audio and Image Processing IP ...
Beaverton, OR · On-site
$120 - $150/hr
Description As a formal verification engineer working the complete formal verification for single or multiple design blocks and IP's (CPU, Cellular and Connectivity IP, Audio and Image Processing IP ...
$184K - $324K/yr
Description As a formal verification engineer working the complete formal verification for single or multiple design blocks and IP's (CPU, Cellular and Connectivity IP, Audio and Image Processing IP ...
$184K - $324K/yr
Description As a formal verification engineer working the complete formal verification for single or multiple design blocks and IP's (CPU, Cellular and Connectivity IP, Audio and Image Processing IP ...
$150K - $277K/yr
Description As a formal verification engineer working the complete formal verification for single or multiple design blocks and IP's (CPU, Cellular and Connectivity IP, Audio and Image Processing IP ...
$150K - $277K/yr
Description As a formal verification engineer working the complete formal verification for single or multiple design blocks and IP's (CPU, Cellular and Connectivity IP, Audio and Image Processing IP ...
$115K - $194K/yr
Description As a formal verification engineer working the complete formal verification for single or multiple design blocks and IPs (CPU, Cellular and Connectivity IP, Audio and Image Processing IP ...
$115K - $194K/yr
Description As a formal verification engineer working the complete formal verification for single or multiple design blocks and IPs (CPU, Cellular and Connectivity IP, Audio and Image Processing IP ...
$115K - $194K/yr
Description As a formal verification engineer working the complete formal verification for single or multiple design blocks and IPs (CPU, Cellular and Connectivity IP, Audio and Image Processing IP ...
$115K - $194K/yr
Description As a formal verification engineer working the complete formal verification for single or multiple design blocks and IPs (CPU, Cellular and Connectivity IP, Audio and Image Processing IP ...
$80K - $91.2K
1% of jobs
$91.2K - $102.5K
1% of jobs
$102.5K - $113.7K
1% of jobs
$113.7K - $124.9K
1% of jobs
$131.5K is the 25th percentile. Wages below this are outliers.
$124.9K - $136.1K
35% of jobs
The median wage is $138.3K / yr.
$136.1K - $147.4K
54% of jobs
$147.4K - $158.6K
1% of jobs
$158.6K - $169.8K
1% of jobs
$169.8K - $181K
2% of jobs
$181K - $192.3K
1% of jobs
$192.3K - $203.5K
1% of jobs
$80K
$142.6K
$203.5K
A Formal Verification Engineer is responsible for ensuring the correctness of hardware or software designs using mathematical and logical techniques. They apply formal methods to verify that a system behaves as intended, identifying potential design flaws early in the development process. This involves writing formal properties, using model checking tools, and collaborating with design and validation teams. Their work helps improve reliability, reduce bugs, and enhance the efficiency of verification compared to traditional simulation-based methods.
As a Formal Verification Engineer, your typical day involves creating and analyzing formal properties, developing assertions, and using formal verification tools to mathematically prove correctness of hardware designs. You'll collaborate closely with design and simulation teams to review specifications, identify verification requirements, and debug issues found during the verification process. Regular documentation of findings, participation in code and design reviews, and ongoing learning about new verification methodologies are also important parts of the role. This dynamic environment requires both technical depth and proactive teamwork to ensure high-quality design outcomes.
To thrive as a Formal Verification Engineer, you need a strong background in digital design, computer architecture, and logic, typically supported by a degree in electrical engineering, computer science, or a related field. Expertise in formal verification tools such as Cadence JasperGold, Synopsys VC Formal, or Mentor Questa, along with proficiency in hardware description languages (HDLs) like Verilog or VHDL, is essential. Strong analytical thinking, attention to detail, and effective communication skills help you collaborate with design and verification teams and present complex findings. These competencies are critical for ensuring hardware systems are bug-free, reliable, and meet stringent industry standards.
Cities with the most Formal Verification Engineer job openings:
The most popular types of Formal Verification Engineer jobs are:
States with the most job openings for Formal Verification Engineer jobs include:
The top searched job categories for Formal Verification Engineer jobs are:
$150 - $350/hr
Other
Medical, Dental, Vision, Retirement, PTO
Re-posted 11 days ago
ChipAgents is revolutionizing chip design and verification with agentic-AI workflows. Founded by experts in AI and semiconductor design, we partner with top-10 semiconductor companies, hyperscale cloud providers, and cutting-edge startups. Our platform accelerates RTL development, functional verification, and simulation—unlocking new levels of productivity and design quality.
Role OverviewWe are seeking a highly capable Formal Verification Engineer to join our core product and research team. In this role, you will work closely with our AI engineering, research, and EDA teams to build advanced agentic AI systems for semiconductor verification.
Your expertise in formal methods, property specification, assertion-based verification, and proof debugging will help shape how AI systems reason about complex hardware behavior. You will play a central role in teaching our AI agents how verification engineers develop properties, analyze counterexamples, close proof convergence gaps, and validate RTL designs with mathematical rigor.
This is a unique opportunity to apply deep formal verification expertise at the frontier of AI-assisted chip design.
Collaborate with AI engineers and researchers to model and codify formal verification workflows.
Develop, refine, and debug SystemVerilog Assertions, formal properties, assumptions, constraints, and coverage objectives.
Use formal verification tools to analyze RTL designs, prove design correctness, and identify functional bugs.
Create reusable formal verification examples, design patterns, proof strategies, and edge cases to train and evaluate AI agents.
Help AI systems interpret design specifications, generate properties, reason about RTL behavior, and debug counterexamples.
Support benchmarking and evaluation of AI-assisted formal verification productivity across realistic IP and SoC verification tasks.
Work closely with customers, product, and research teams to translate formal verification pain points into automated AI workflows.
Contribute to methodology development for assertion-based verification, formal apps, equivalence checking, connectivity checking, and coverage closure.
Strong expertise in formal verification methodologies and signoff flows.
Hands-on experience with JasperGold, VC Formal, Questa Formal, or equivalent tools.
Deep knowledge of SystemVerilog Assertions (SVA) and assertion-based verification.
Experience proving complex properties, debugging counterexamples, and achieving formal closure.
Familiarity with SAT/SMT-based reasoning and formal verification fundamentals.
Experience with CDC, RDC, lint, and static verification methodologies.
Strong RTL design and microarchitecture understanding.
Experience verifying production IPs, subsystems, or SoCs.
Proficiency in Python, Tcl, or scripting for verification automation.
Interest in applying AI/LLMs to hardware design and verification workflows
Work at the frontier of AI and semiconductor design.
Collaborate with a world-class team spanning AI, systems, and EDA.
Shape a foundational shift in how chips are built.
$150K/yr – $350K/yr + Offers Equity. We are open to discuss above-scale compensation with exceptional candidates on a case-by-case basis.
Unlimited PTO and full benefits (medical, vision, dental, 401k).
Two engineering-centric offices with free parking, private gym, and free lunch, drinks and snacks.
