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Pre Silicon Verification Engineer Jobs (NOW HIRING)

GPU DFT Design Verification Engineer

Austin, TX · On-site

$134.80K - $164.50K/yr

The DFT Design Verification Engineer will be on a team which is responsible for the complete DFT pre-silicon verification and support for silicon bring-up of GPU core. As a DFT Verification engineer ...

GPU DFT Design Verification Engineer

Austin, TX · On-site

$134.80K - $164.50K/yr

The DFT Design Verification Engineer will be on a team which is responsible for the complete DFT pre-silicon verification and support for silicon bring-up of GPU core. As a DFT Verification engineer ...

GPU DFT Design Verification Engineer

Austin, TX · On-site

$134.80K - $164.50K/yr

The DFT Design Verification Engineer will be on a team which is responsible for the complete DFT pre-silicon verification and support for silicon bring-up of GPU core. In this highly transparent and ...

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Pre Silicon Verification Engineer information

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$80K

$142.6K

$203.5K

How much do pre silicon verification engineer jobs pay per year?

As of May 31, 2026, the average yearly pay for pre silicon verification engineer in the United States is $142,619.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $136,000.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a Pre Silicon Verification Engineer, and why are they important?

To thrive as a Pre Silicon Verification Engineer, you need a strong background in digital design principles, hardware description languages like Verilog or VHDL, and typically a degree in electrical or computer engineering. Experience with verification methodologies such as UVM, scripting languages (Python, Perl), and simulation tools like ModelSim or VCS is commonly required. Attention to detail, analytical thinking, and effective teamwork are vital soft skills for debugging complex systems and collaborating with design teams. These skills ensure robust verification processes, reducing design errors and enabling successful chip development before manufacturing.

How does a Pre Silicon Verification Engineer typically collaborate with design and validation teams during a project?

Pre Silicon Verification Engineers work closely with both design and validation teams to ensure that new hardware designs function as intended before manufacturing. They regularly participate in design reviews, clarify specifications, and provide feedback on testability and potential design issues. Effective collaboration often involves daily stand-up meetings, shared documentation, and synchronized test planning to align verification strategies with the evolving design. This cross-functional teamwork is essential for identifying bugs early and streamlining the development cycle.

What are Pre Silicon Verification Engineers?

Pre Silicon Verification Engineers are professionals who ensure that integrated circuit (IC) designs function correctly before they are manufactured into silicon chips. They use simulation, modeling, and various verification methodologies to identify and fix design errors early in the development process. Their work helps reduce costly mistakes and ensures that the final hardware meets all functional and performance requirements. These engineers collaborate closely with design, validation, and hardware teams throughout the product development lifecycle.

What is the difference between Pre Silicon Verification Engineer vs Digital Verification Engineer?

AspectPre Silicon Verification EngineerDigital Verification Engineer
CredentialsBachelor's or Master's in Electrical Engineering or Computer EngineeringBachelor's or Master's in Electrical Engineering or Computer Engineering
Work EnvironmentDesign teams, FPGA labs, simulation environmentsSimulation platforms, test benches, FPGA/ASIC labs
Industry UsageSemiconductor, chip design, hardware developmentASIC/FPGA design, hardware verification, chip development

Pre Silicon Verification Engineers focus on verifying hardware designs before silicon fabrication, often using simulation and emulation tools. Digital Verification Engineers also verify digital hardware but may work across a broader range of digital systems, including post-silicon validation. Both roles require similar skills and credentials, but their specific tasks and focus areas differ within the hardware development process.

More about Pre Silicon Verification Engineer jobs
What cities are hiring for Pre Silicon Verification Engineer jobs? Cities with the most Pre Silicon Verification Engineer job openings:
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What job categories do people searching Pre Silicon Verification Engineer jobs look for? The top searched job categories for Pre Silicon Verification Engineer jobs are:
Infographic showing various Pre Silicon Verification Engineer job openings in the United States as of May 2026, with employment types broken down into 56% Full Time, and 44% Part Time. Highlights an 97% Physical, 2% Hybrid, and 1% Remote job distribution, with an average salary of $142,619 per year, or $68.6 per hour.

Pre-Silicon Verification Engineer

Sumeru Solutions

Santa Clara, CA

$159.70K/yr

Contractor

Posted 21 days ago


Job description

Company Description

Sumeru has been in the IT Business for more than a decade. Clients across 22 countries turn to us for their Web Application Services, Information Security and Business Process Management needs. We are Microsoft Gold Certified partners and also an ISO 270001 certified company. 

Job Description

Hello Gerald,

We are sourcing for Pre-Silicon Verification Engineer with one of our Direct Client in Santa Clara, CA. Please go through to the job description below and of you feel comfortable with the Required skills and responsibilities, please reply me back with your updated word doc resume and Table with your details to vinay.shrivas AT sumerusolutions.com or contact me for more details at 571-250-5780.

Project Details:

Job Title : Pre-Silicon Verification Engineer

Client Location : Santa Clara, CA

Project Duration : Long term (6 - 12 + months Contract )

Responsibilities

1) Pre-silicon Verification expertise

2) SystemVerilog experience

3) Importantly someone who is familiar with power management verification (we use SYNP UPF flow).

4) This person should be able to work in Santa Clara and ASAP (preferably next week itself).


Submission

Candidate Name

Present location (city, state or ZIP)

Preferred Base Location

Work Authorization

Tel No

Email ID

*Joining availability (post-selection)

Overall relevant experience of candidate

Current Salary

Expected Rate/Salary - $$/HR/K

Do you have 4 year degree (Y/N)

Ready to Travel (Y/N)

Where would you stand in scale of 1-10 for this req

Qualifications

Additional qualifications include:

- Strong SOC/CPU microarchitecture and/or system level skills with five to seven years of pre-si verification background

- Experience with logic design and validation tools and methodologies including: Verilog, System Verilog, OVM/UVM, Synopsys VCS

- Familiarity of power management flows

- Knowledge of assertion based languages and/or methodology and C/C++ would be an added advantage

- Knowledge of emulation platforms a plus

- Experience in automation using Perl is desirable

- Demonstrate capability to ramp on any Industry standard device protocols and architecture

- Need to have demonstrated excellence in problem solving and resolution through innovative methods in environment/tools capabilities, test plan and test development, debug, automation, etc.

Additional Information

All your information will be kept confidential according to EEO guidelines.