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Pre Silicon Verification Engineer Jobs (NOW HIRING)

Apple

GPU DFT Design Verification Engineer

Austin, TX · On-site

$134.80K - $164.50K/yr

The DFT Design Verification Engineer will be on a team which is responsible for the complete DFT pre-silicon verification and support for silicon bring-up of GPU core. As a DFT Verification engineer ...

Apple

GPU DFT Design Verification Engineer

Austin, TX · On-site

$134.80K - $164.50K/yr

The DFT Design Verification Engineer will be on a team which is responsible for the complete DFT pre-silicon verification and support for silicon bring-up of GPU core. As a DFT Verification engineer ...

Apple

GPU DFT Design Verification Engineer

Austin, TX · On-site

$134.80K - $164.50K/yr

The DFT Design Verification Engineer will be on a team which is responsible for the complete DFT pre-silicon verification and support for silicon bring-up of GPU core. In this highly transparent and ...

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Pre Silicon Verification Engineer information

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$80K

$142.6K

$203.5K

How much do pre silicon verification engineer jobs pay per year?

As of May 31, 2026, the average yearly pay for pre silicon verification engineer in the United States is $142,619.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $136,000.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a Pre Silicon Verification Engineer, and why are they important?

To thrive as a Pre Silicon Verification Engineer, you need a strong background in digital design principles, hardware description languages like Verilog or VHDL, and typically a degree in electrical or computer engineering. Experience with verification methodologies such as UVM, scripting languages (Python, Perl), and simulation tools like ModelSim or VCS is commonly required. Attention to detail, analytical thinking, and effective teamwork are vital soft skills for debugging complex systems and collaborating with design teams. These skills ensure robust verification processes, reducing design errors and enabling successful chip development before manufacturing.

How does a Pre Silicon Verification Engineer typically collaborate with design and validation teams during a project?

Pre Silicon Verification Engineers work closely with both design and validation teams to ensure that new hardware designs function as intended before manufacturing. They regularly participate in design reviews, clarify specifications, and provide feedback on testability and potential design issues. Effective collaboration often involves daily stand-up meetings, shared documentation, and synchronized test planning to align verification strategies with the evolving design. This cross-functional teamwork is essential for identifying bugs early and streamlining the development cycle.

What are Pre Silicon Verification Engineers?

Pre Silicon Verification Engineers are professionals who ensure that integrated circuit (IC) designs function correctly before they are manufactured into silicon chips. They use simulation, modeling, and various verification methodologies to identify and fix design errors early in the development process. Their work helps reduce costly mistakes and ensures that the final hardware meets all functional and performance requirements. These engineers collaborate closely with design, validation, and hardware teams throughout the product development lifecycle.

What is the difference between Pre Silicon Verification Engineer vs Digital Verification Engineer?

AspectPre Silicon Verification EngineerDigital Verification Engineer
CredentialsBachelor's or Master's in Electrical Engineering or Computer EngineeringBachelor's or Master's in Electrical Engineering or Computer Engineering
Work EnvironmentDesign teams, FPGA labs, simulation environmentsSimulation platforms, test benches, FPGA/ASIC labs
Industry UsageSemiconductor, chip design, hardware developmentASIC/FPGA design, hardware verification, chip development

Pre Silicon Verification Engineers focus on verifying hardware designs before silicon fabrication, often using simulation and emulation tools. Digital Verification Engineers also verify digital hardware but may work across a broader range of digital systems, including post-silicon validation. Both roles require similar skills and credentials, but their specific tasks and focus areas differ within the hardware development process.

More about Pre Silicon Verification Engineer jobs
What cities are hiring for Pre Silicon Verification Engineer jobs? Cities with the most Pre Silicon Verification Engineer job openings:
What states have the most Pre Silicon Verification Engineer jobs? States with the most job openings for Pre Silicon Verification Engineer jobs include:
What job categories do people searching Pre Silicon Verification Engineer jobs look for? The top searched job categories for Pre Silicon Verification Engineer jobs are:
Pre Silicon Verification Engineer jobs near you
Infographic showing various Pre Silicon Verification Engineer job openings in the United States as of May 2026, with employment types broken down into 56% Full Time, and 44% Part Time. Highlights an 97% Physical, 2% Hybrid, and 1% Remote job distribution, with an average salary of $142,619 per year, or $68.6 per hour.
Pre-Silicon Verification Engineer

Pre-Silicon Verification Engineer

Apex Informatics

Los Altos, CA • On-site

$160.80K/yr

Full-time

Posted 2 hours ago

Job description

Pre-Silicon Verification Engineer for AI
Duration: 6 months +
Work Location: Los Altos, CA
Onsite no exceptions.
Location: Los Altos, CA
Candidate Type: EAD, Green Card, TN VISA, or US Citizens
Jobsite: Onsite 5 days per week
Job Type: Contract to Hire or FTE
Duration: 6 months
Candidate must be willing to convert
Role Description:
We are looking for an experienced, highly skilled, and motivated Pre-Silicon Verification Engineer to join our core team. In this role, you will be responsible for chip-level and performance verification of one of our custom ASICs.
Mandatory Requirements:
  • Bachelor's or master's in computer science, Computer Engineering, or a related field from a recognized university
  • Expert-level experience with simulation tools & flows (VCS, Verdi, NCSim and the like)
  • Scripting experience in Perl and/or Python
  • 5+ years' experience using constrained random & functional coverage-based verification methodologies on large design blocks
  • 5+ years hands-on coding of UVM verification environments
  • C/C++ expertise
  • Excellent communication skills and a strong track record of cross-functional collaboration
  • Must have Experience with and understanding of common LLMs
  • Experience with AI or other large-scale datacenter-grade ASICs
  • Experience doing performance verification of compute or networking ASICs

Candidate Daily Activities"
  • Work with our engineers and partners to help verify our ASICs
  • Work with our architecture team to understand our architecture and to design end-to-end test flows and methodologies to verify real-world performance scenarios
Manage vendors and/or contractors as necessary

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