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Formal Verification Engineer Jobs in New York (NOW HIRING)

Airspan

UVM SYSTEMVERILOG VERIFICATION ENGINEER

Warren, NJ · On-site

$141K/yr

Airspan Careers UVM SYSTEMVERILOG VERIFICATION ENGINEER Location: Warren, New Jersey, Plano, TX or ... Familiarity with debugging tools, coverage metrics, and formal verification techniques. * Strong ...

Cogent Security

AI Research Engineer

Manhattan, NY · On-site

The AI Research Engineer will conduct original research in automated reasoning and AI-driven code ... Hands-on experience with static/dynamic analysis, formal verification, and/or automated testing and ...

PulseRise Technologies

Protocol Engineer

New York, NY · On-site

... formal verification or advanced security tooling Deep understanding of blockchain architecture and ... engineer Smart contract design and security assessment (live and/or take-home) Onsite in NYC ...

fun.xyz

Protocol Engineer

New York, NY · On-site

While this unlocks more open and programmable financial systems, it also introduces significant ... Experience with formal verification or advanced smart contract testing frameworks We may use ...

fun.xyz

Protocol Engineer

New York, NY

While this unlocks more open and programmable financial systems, it also introduces significant ... Experience with formal verification or advanced smart contract testing frameworks We may use ...

fun.xyz

Protocol Engineer

New York, NY

While this unlocks more open and programmable financial systems, it also introduces significant ... Experience with formal verification or advanced smart contract testing frameworks We may use ...

Peraton

Software Integration Engineer

Red Bank, NJ · On-site

$106K - $143K/yr

This engineer will implement CI/CD pipelines, build and debug Docker containers, write integration ... Experience with formal verification or formal methods tools (SMT solvers such as Z3, property-based ...

Peraton

Software Integration Engineer

Red Bank, NJ · On-site

$104K - $166K/yr

This engineer will implement CI/CD pipelines, build and debug Docker containers, write integration ... Experience with formal verification or formal methods tools (SMT solvers such as Z3, property-based ...

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Formal Verification Engineer information

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How much do formal verification engineer jobs pay per year?

As of Aug 15, 2026, the average yearly pay for formal verification engineer in New York is $156,030.00, according to ZipRecruiter salary data. Most workers in this role earn between $148,800.00 and $148,800.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a formal verification engineer?

To thrive as a Formal Verification Engineer, you need a strong background in digital design, computer architecture, and logic, typically supported by a degree in electrical engineering, computer science, or a related field. Expertise in formal verification tools such as Cadence JasperGold, Synopsys VC Formal, or Mentor Questa, along with proficiency in hardware description languages (HDLs) like Verilog or VHDL, is essential. Strong analytical thinking, attention to detail, and effective communication skills help you collaborate with design and verification teams and present complex findings. These competencies are critical for ensuring hardware systems are bug-free, reliable, and meet stringent industry standards.

What are the common daily responsibilities of a formal verification engineer?

As a Formal Verification Engineer, your typical day involves creating and analyzing formal properties, developing assertions, and using formal verification tools to mathematically prove correctness of hardware designs. You'll collaborate closely with design and simulation teams to review specifications, identify verification requirements, and debug issues found during the verification process. Regular documentation of findings, participation in code and design reviews, and ongoing learning about new verification methodologies are also important parts of the role. This dynamic environment requires both technical depth and proactive teamwork to ensure high-quality design outcomes.

What is a formal verification engineer?

A Formal Verification Engineer is responsible for ensuring the correctness of hardware or software designs using mathematical and logical techniques. They apply formal methods to verify that a system behaves as intended, identifying potential design flaws early in the development process. This involves writing formal properties, using model checking tools, and collaborating with design and validation teams. Their work helps improve reliability, reduce bugs, and enhance the efficiency of verification compared to traditional simulation-based methods.

What are the most commonly searched types of Formal Verification Engineer jobs in New York?

The most popular types of Formal Verification Engineer jobs in New York are:

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For Formal Verification Engineer jobs in New York, the most frequently searched job titles are:

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Formal Verification Engineer jobs near you
Infographic showing various Formal Verification Engineer job openings in New York as of August 2026, with employment types broken down into 83% Full Time, and 17% Contract. Highlights an 66% In-person, 17% Hybrid, and 17% Remote job distribution, with an average salary of $156,030 per year, or $75 per hour.

UVM SYSTEMVERILOG VERIFICATION ENGINEER

Airspan

Warren, NJ • On-site

$141K/yr

Full-time

Re-posted 7 days ago

Job description

Airspan Careers
UVM SYSTEMVERILOG VERIFICATION ENGINEER
Location: Warren, New Jersey, Plano, TX or REMOTE U.S.
Company: AirSpan Networks
About AirSpan
AirSpan Networks is a global provider of innovative 4G and 5G network solutions, enabling efficient and cost-effective connectivity for operators, enterprises, and industrial applications. We are looking for a skilled UVM SystemVerilog Verification Engineer to join our dynamic team and contribute to the validation and testing of our cutting-edge communication technologies.
Job Description
As a UVM Verification Engineer, you will be responsible for developing and executing test plans using Universal Verification Methodology (UVM) to validate the functionality, performance, and reliability of AirSpan's ASIC and FPGA designs. You will work closely with design and development teams to ensure compliance with specifications and industry standards.
Key Responsibilities
  • Develop and implement UVM-based verification plans and test strategies for FPGA designs.
  • Perform functional, system-level, and regression testing for digital hardware components.
  • Create test benches, test cases, and automation frameworks in System Verilog.
  • Analyze test results, debug issues, and collaborate with design teams to resolve defects.
  • Ensure compliance with industry standards and customer requirements.
  • Provide documentation and reports on test procedures, results, and defect tracking.
  • Continuously optimize test processes and tools to improve efficiency and accuracy.

Qualifications & Experience
  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related fields.
  • 10 years of experience in UVM-based verification of FPGA systems.
  • Strong understanding of SystemVerilog and Universal Verification Methodology (UVM).
  • Proficiency in scripting languages such as Python or Perl for automation.
  • Experience with simulation tools such as ModelSim or QuestaSim.
  • Experience with C/C++
  • Experience in implementing Bit Accurate Models and debugging DSP designs
  • Familiarity with debugging tools, coverage metrics, and formal verification techniques.
  • Strong problem-solving and analytical skills with attention to detail.
  • Knowledge of O-RAN architecture and protocols for 4G and 5G networks.
  • Ability to work collaboratively in a fast-paced, cross-functional team environment.
  • Design experience a plus.

Preferred Skills
  • Experience in verification of communication protocols.
  • Knowledge of FPGA development and hardware description languages such as VHDL/Verilog.
  • Understanding of hardware/software co-verification techniques.

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