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Design Verification Engineer Jobs in New York (NOW HIRING)

Airspan

UVM SYSTEMVERILOG VERIFICATION ENGINEER

Warren, NJ · On-site

$141K/yr

You will work closely with design and development teams to ensure compliance with specifications ... Engineering, or related fields. * 10 years of experience in UVM-based verification of FPGA systems.

JS Consulting

Senior Verification Engineer

New York, NY · On-site

$114K - $157K/yr

Job Title- Senior Verification Engineer Project Location - On-site 5 days Lake Ronkonkoma NY (Long ... Solid understanding of FPGA architecture and digital design. * Hands-on experience with PCIe, 1G ...

Normal Computing

Founding Data Engineer

New York, NY · On-site

$275K - $340K/yr

The Role Our EDA tool accelerates the design and verification of silicon. It integrates with the engineer's workflow to assist with design, verification, and debugging, and uses AI to generate ...

Airspan

FPGA DESIGN ENGINEER

Warren, NJ · On-site

$127K - $176K/yr

You will work closely with system architects, software engineers, and verification engineers to develop high-performance digital hardware solutions. Key Responsibilities: * Design and implement FPGA ...

Normal Computing

Hardware Engineer, RTL

New York, NY · On-site

$200K - $285K/yr

The Role As an RTL Design Engineer at Normal, you will design and verify the digital logic at the heart of Normal's thermodynamic hardware. This work sits at the intersection of classical ASIC design ...

OrganOx

Mechanical Design Engineer

Madison, NJ · On-site

$78K - $106K/yr

... design verification and validation • Collaborating with manufacturing and suppliers to ensure ... engineering documentation in accordance with ISO 13485 and other applicable standards • ...

OrganOx

Mechanical Design Engineer

Madison, NJ · On-site

$78K - $106K/yr

... design verification and validation • Collaborating with manufacturing and suppliers to ensure ... engineering documentation in accordance with ISO 13485 and other applicable standards • ...

Jane Street

ASIC Engineer

New York, NY

$181K/yr

Have 4+ years practical experience in RTL design and verification * Experienced in ASIC design ... Interested in using software engineering techniques to improve the hardware design process, and ...

Jane Street

ASIC Engineer

New York, NY · On-site

$181K/yr

Have 4+ years practical experience in RTL design and verification * Experienced in ASIC design ... Interested in using software engineering techniques to improve the hardware design process, and ...

Clarapath Inc

Electrical Engineer

Hawthorne, NY

$95K - $135K/yr

Support prototype builds, design verification testing (DVT), production validation, and manufacturing transfers * Collaborate with Manufacturing Engineering to improve product manufacturability ...

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Design Verification Engineer information

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$115.4K

$163.2K

$182.7K

How much do design verification engineer jobs pay per year?

As of Jul 29, 2026, the average yearly pay for design verification engineer in New York is $163,175.00, according to ZipRecruiter salary data. Most workers in this role earn between $148,800.00 and $181,600.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive in the Design Verification Engineer position, and why are they important?

Design Verification Engineers require a solid background in digital design concepts, computer engineering, and electrical engineering, usually supported by a relevant bachelor’s or master’s degree. Expertise with hardware description languages like Verilog or VHDL, simulation tools, and familiarity with Unix/Linux environments are typical technical requirements, with certifications in FPGA/ASIC design considered advantageous. Strong analytical thinking, problem-solving skills, teamwork, and effective communication help these engineers collaborate closely with design, validation, and development teams. These competencies are vital to ensuring design correctness, catching flaws early, and driving efficient, reliable hardware development.

What is a Design Verification Engineer job?

A Design Verification Engineer ensures that hardware designs function correctly by developing and executing test plans, writing verification code (often in SystemVerilog with UVM), and debugging design issues. They work closely with design and validation teams to confirm specifications are met before manufacturing. Their role is critical in preventing costly design flaws and ensuring high-quality semiconductor products.

What are the most common challenges faced by Design Verification Engineers in their daily work?

Design Verification Engineers often face the challenge of thoroughly validating complex digital designs within tight project deadlines. Debugging intricate issues, dealing with evolving specifications, and ensuring complete coverage during simulation can require a great deal of attention to detail and persistence. Collaboration with designers, validation teams, and often cross-functional groups is critical to resolving ambiguities and preventing errors from reaching production. Adapting to new verification methodologies or tools is also common as technologies and standards advance. These challenges offer valuable learning opportunities and play a crucial role in producing robust, high-quality hardware products.

What are the most commonly searched types of Design Verification Engineer jobs in New York? The most popular types of Design Verification Engineer jobs in New York are:
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What are popular job titles related to Design Verification Engineer jobs in NY? For Design Verification Engineer jobs in NY, the most frequently searched job titles are:
Design Verification Engineer jobs near you
Infographic showing various Design Verification Engineer job openings in New York as of July 2026, with employment types broken down into 89% Full Time, and 11% Contract. Highlights an 100% In-person job distribution, with an average salary of $163,175 per year, or $78.4 per hour.

Design Verification Engineer

Normal Computing

New York, NY • On-site

$140K - $180K/yr

Full-time

Re-posted 24 days ago

Job description

About Normal Computing
Normal Computing builds silicon that turns thermal noise from an obstacle into a computational resource. Conventional chips spend most of their energy forcing determinism onto physics; ours compute with it. Stochastic, in-memory, asynchronous: the result is 10-100× more AI inference per dollar, per watt.
We co-design the full stack: AI-native EDA systems in production with the world's largest semiconductor companies, and the advanced ASICs they make possible. Backed by $85M+ from the world's leading deep-tech investors and built by scientists, engineers, and operators from the labs that built modern computing.
Normal works as one team across New York, Silicon Valley, London, Copenhagen, and Seoul. We hire people who want the hardest version of their craft, across every discipline, at every seniority.
The Role
As a Design Verification Engineer at Normal, you will verify our own physics-inspired ASICs on the road to tapeout, and set the quality bar for what our AI learns: reviewing generated verification collateral and shaping the standards our models train against. From time to time, you may also be tapped to support a customer deployment alongside our forward-deployed team, where your verification credibility helps our AI platform land inside real DV flows. The through-line is your DV expertise, applied to silicon that computes differently than anything you've verified before, and to the AI that is changing how verification gets done. This is a seat for a verification engineer who wants their craft to compound rather than repeat.
What You Will Own
  • Thermodynamic ASIC Verification: Own design verification for Normal's internal silicon: testbench environments, assertions, and coverage from design documents through functional coverage and closure, supporting the program to tapeout.
  • AI Product Refinement: Review AI-generated verification collateral to shape product strategy and tool usability in collaboration with the ML and product teams.
  • Data Quality Bar: Set the quality standard for verification training data: define rubrics, curate golden examples, and partner with our Data team, who own the pipelines, so our models learn from verification artifacts a real DV engineer would sign off on.
  • Deployment Support: When needed, support customer engagements alongside our forward-deployed team: validating AI-generated collateral against real customer specifications and lending DV credibility to deployments.
  • Tooling: Set up and evaluate EDA tools, ensuring usability and effective deployment on shared computing resources internally and in customer environments.

What Makes You a Great Fit
  • 5+ years of experience in digital verification at a major semiconductor or EDA tool company
  • Advanced proficiency in SystemVerilog, UVM methodology, and EDA verification tools (vManager, Xcelium, Jasper), with strong Python or Perl scripting
  • Proven expertise in end-to-end design verification, including test plan creation, stimulus generation, and feature extraction
  • Willingness to occasionally support customer-facing deployment work, including some travel
  • Excellent written and spoken communication skills: you can hold the room with a customer's verification lead as credibly as you hold a debug session

Bonus Points
  • Experience in a customer-facing, field-application, or forward-deployed engineering role at a semiconductor or EDA company
  • Hands-on use of LLMs or agentic tools in verification workflows
  • Exposure to analog, mixed-signal, or unconventional compute verification

Equal Employment Opportunity Statement
Normal Computing is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other legally protected status.
Accessibility Accommodations
Normal Computing is committed to providing reasonable accommodations to individuals with disabilities. If you need assistance or an accommodation due to a disability, please let us know at accommodations@normalcomputing.com.
Privacy Notice
By submitting your application, you agree that Normal Computing may collect, use, and store your personal information for employment-related purposes in accordance with our Privacy Policy.

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