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Design Verification Engineer Jobs in New York (NOW HIRING)

Normal Computing

Hardware Engineer, RTL

New York, NY · On-site

$200K - $400K/yr

The Role As an RTL Design Engineer at Normal, you will design and verify the digital logic at the heart of Normal's thermodynamic hardware. This work sits at the intersection of classical ASIC design ...

OrganOx

Mechanical Design Engineer

Madison, NJ · On-site

$78K - $106K/yr

Supporting engineering analysis and testing activities to aid design verification and validation * Collaborating with manufacturing and suppliers to ensure designs are practical and manufacturable

OrganOx

Mechanical Design Engineer

Madison, NJ · On-site

$78K - $106K/yr

... design verification and validation • Collaborating with manufacturing and suppliers to ensure ... engineering documentation in accordance with ISO 13485 and other applicable standards • ...

Redolent, Inc.

US_West | Infrastructure Engineer_L3

NJ · On-site

$110K - $144K/yr

Verification Infrastructure Engineer Work Location: San Francisco, CA / Seattle, WA / Santa Clara, CA CAD/EDA - Silicon Design/Verification Infrastructure Minimum Qualifications: Minimum 5 years of ...

Mercury Systems

Mechanical Design Engineering III

Caldwell, NJ · On-site

$82K - $111K/yr

The ideal engineer will demonstrate strong cross-functional collaboration skills, while working ... Support product verification testing including thermal, vibration, mechanical shock, humidity, and ...

mercury

Mechanical Design Engineering III

West Caldwell, NJ · Hybrid

$82K - $111K/yr

The ideal engineer will demonstrate strong cross-functional collaboration skills, while working ... Support product verification testing including thermal, vibration, mechanical shock, humidity, and ...

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All JobsDesign Verification Engineer JobsDesign Verification Engineer Jobs in New York

Design Verification Engineer information

See New York salary details

$115.4K

$163.2K

$182.7K

How much do design verification engineer jobs pay per year?

As of Sep 7, 2026, the average yearly pay for design verification engineer in New York is $163,175.00, according to ZipRecruiter salary data. Most workers in this role earn between $148,800.00 and $181,600.00 per year, depending on experience, location, and employer.

What is a design verification engineer?

A Design Verification Engineer ensures that hardware designs function correctly by developing and executing test plans, writing verification code (often in SystemVerilog with UVM), and debugging design issues. They work closely with design and validation teams to confirm specifications are met before manufacturing. Their role is critical in preventing costly design flaws and ensuring high-quality semiconductor products.

What skills and qualifications are needed to be a design verification engineer?

Design Verification Engineers require a solid background in digital design concepts, computer engineering, and electrical engineering, usually supported by a relevant bachelor’s or master’s degree. Expertise with hardware description languages like Verilog or VHDL, simulation tools, and familiarity with Unix/Linux environments are typical technical requirements, with certifications in FPGA/ASIC design considered advantageous. Strong analytical thinking, problem-solving skills, teamwork, and effective communication help these engineers collaborate closely with design, validation, and development teams. These competencies are vital to ensuring design correctness, catching flaws early, and driving efficient, reliable hardware development.

What are the most common challenges faced by design verification engineers in their daily work?

Design Verification Engineers often face the challenge of thoroughly validating complex digital designs within tight project deadlines. Debugging intricate issues, dealing with evolving specifications, and ensuring complete coverage during simulation can require a great deal of attention to detail and persistence. Collaboration with designers, validation teams, and often cross-functional groups is critical to resolving ambiguities and preventing errors from reaching production. Adapting to new verification methodologies or tools is also common as technologies and standards advance. These challenges offer valuable learning opportunities and play a crucial role in producing robust, high-quality hardware products.

What are the most commonly searched types of Design Verification Engineer jobs in New York?

The most popular types of Design Verification Engineer jobs in New York are:

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Design Verification Engineer jobs near you
Infographic showing various Design Verification Engineer job openings in New York as of August 2026, with employment types broken down into 46% Full Time, and 54% Contract. Highlights an 100% In-person job distribution, with an average salary of $163,175 per year, or $78.4 per hour.

Hardware Engineer, RTL

Normal Computing

New York, NY • On-site

$200K - $400K/yr

Full-time

Re-posted 5 days ago

Key responsibilities

  • Design and verify digital logic at the microarchitecture level, including writing synthesizable SystemVerilog RTL.

  • Collaborate with architecture, verification, and physical design teams to ensure design meets specifications, timing, and area constraints.

  • Support tapeout preparation, integration, and post-silicon bring-up activities.

Job description

Normal Computing | Build with Us
Normal is an applied AI company solving the hardest problems in AI and silicon. We build foundational hardware and software for the semiconductor industry, critical AI infrastructure, and the broader systems that power our world, in partnership with the world's most advanced institutions. We work as one team across New York City, San Francisco, London, Copenhagen, and Pangyo.
The Role
As an RTL Design Engineer at Normal, you will design and verify the digital logic at the heart of Normal's thermodynamic hardware. This work sits at the intersection of classical ASIC design, novel computing architectures, and a development environment where the hardware and the algorithms are built together, not in sequence.
You will own RTL from microarchitecture to tapeout: writing microarchitecture specifications, creating synthesizable SystemVerilog, working with design verification engineers fully test the design using conventional and formal methods, and working closely with physical design to make sure the design meets area and timing constraints. Because Normal's chips are not standard accelerators, the RTL engineer here is closer to first-principles decisions than at a larger company. You will be shaping architecture, not just implementing it.
This is a role for an engineer who collaborates effectively across teams, including architecture, verification and physical design. The strongest candidates have taped out silicon, written RTL and helped close coverage, and are comfortable working in an environment where the specification is still being developed in parallel.
What You Will Own
  • RTL Design: Write and own synthesizable RTL in SystemVerilog across blocks ranging from datapath logic to control and memory interfaces.
  • Microarchitecture: Work with architecture to translate high-level specifications into implementable microarchitectures.
  • Verification: Work closely with the verification team to review verification plans, assist on debug, and become a partner in closing coverage.
  • Physical Design Collaboration: Collaborate with physical design on timing closure, floorplanning constraints, and DFT.
  • Design Reviews: Participate in design reviews and contribute to architecture decisions, not just implementation.
  • Tapeout & Bring-up: Support tapeout preparation, integration, and post-silicon bring-up as needed.
What Makes You a Great Fit
  • Hands-on experience writing production RTL in SystemVerilog and closing it through synthesis and place-and-route
  • Experience in closing coverage to a high level
  • At least one tapeout in your background, from any node and any company size
  • Experience working on datapaths, pipelines, or custom logic where the microarchitecture was not fully specified upfront
  • Strong debugging instincts across simulation, waveforms, and formal counterexamples
  • Ability to work directly with architects and physical designers without needing a large intermediary layer
  • Industry experience in ASIC or SoC design
Bonus Points
  • Experience at an AI chip company where design and verification were tightly coupled
  • Open-source RTL contributions to projects like Chipyard, OpenTitan, or CVA6
  • Familiarity with RISC-V or other open ISAs
  • Experience with AI-assisted RTL or EDA tooling in your design workflow
  • Exposure to physical design constraints, floorplanning, or timing-driven RTL development

Equal Employment Opportunity Statement
Normal Computing is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other legally protected status.
Accessibility Accommodations
Normal Computing is committed to providing reasonable accommodations to individuals with disabilities. If you need assistance or an accommodation due to a disability, please let us know at accommodations@normalcomputing.com.
Privacy Notice
By submitting your application, you agree that Normal Computing may collect, use, and store your personal information for employment-related purposes in accordance with our Privacy Policy.

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