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Uvm Verification Engineer Jobs in New York (NOW HIRING)

Airspan

UVM SYSTEMVERILOG VERIFICATION ENGINEER

Warren, NJ · On-site

$141K/yr

Airspan Careers UVM SYSTEMVERILOG VERIFICATION ENGINEER Location: Warren, New Jersey, Plano, TX or REMOTE U.S. Company: AirSpan Networks About AirSpan AirSpan Networks is a global provider of ...

JS Consulting

Senior Verification Engineer

New York, NY · On-site

$114K - $157K/yr

Job Title- Senior Verification Engineer Project Location - On-site 5 days Lake Ronkonkoma NY (Long ... Strong expertise in VHDL, with working knowledge of Verilog/SystemVerilog and UVM. * Proficiency ...

Normal Computing

Forward Deployed Engineer

New York, NY · On-site

$200K - $400K/yr

Direct experience with EDA, semiconductor design flows, verification workflows (UVM, SystemVerilog ... engineering * Built or led an FDE or customer-deployment function from the ground up at an earlier ...

L3HHCM20

Specialist, Electrical Engineer

Clifton, NJ

$92K - $171K/yr

Specialist, Electrical Engineering (FPGA) Job Code: 40150 Job Location: Clifton, NJ Job Schedule: 9 ... Formal FPGA verification experience, UVM, Directed Testing, Code Coverage * Experience with and ...

Normal Computing

Hardware Engineer, FPGA

New York, NY · On-site

$200K - $400K/yr

As our FPGA Design Engineer, you will own the bridge between RTL and physical silicon: bringing our ... Verification frameworks like Cocotb or UVM * Experience deploying ML models to FPGAs (hls4ml, FINN ...

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Uvm Verification Engineer information

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How much do uvm verification engineer jobs pay per year?

As of Aug 31, 2026, the average yearly pay for uvm verification engineer in New York is $156,030.00, according to ZipRecruiter salary data. Most workers in this role earn between $148,800.00 and $148,800.00 per year, depending on experience, location, and employer.

What is a UVM verification engineer?

A UVM Verification Engineer is responsible for verifying the functionality of digital designs using the Universal Verification Methodology (UVM). They develop testbenches, write SystemVerilog test cases, and implement constrained-random and coverage-driven verification techniques. Their role ensures that ASICs or FPGAs meet design specifications before fabrication. They also work with RTL designers to identify and debug issues, improving overall design quality.

What are the typical responsibilities of a UVM verification engineer?

As a Uvm Verification Engineer, your daily responsibilities often include developing and maintaining testbenches using UVM, creating and executing verification plans, writing and debugging test cases in SystemVerilog, and analyzing simulation results to identify design bugs. You’ll typically collaborate closely with design engineers to understand new features and with fellow verification engineers to enhance coverage and test methodology. Regular meetings and status updates are common, ensuring alignment across the verification team and other departments. This dynamic environment offers opportunities to tackle complex debugging challenges and continuously learn as project requirements evolve.

What are the key skills and qualifications needed to thrive as a UVM verification engineer?

To thrive as a Uvm Verification Engineer, you need a strong background in digital design verification, SystemVerilog programming, and a deep understanding of verification methodologies, particularly Universal Verification Methodology (UVM). Proficiency in using simulation tools such as Mentor Questa, Cadence Xcelium, or Synopsys VCS, as well as familiarity with version control and bug tracking systems, is typically required. Strong analytical thinking, effective communication, and teamwork skills set individuals apart in this position. These skills are crucial to ensure high-quality, reliable silicon designs and seamless collaboration across development teams in fast-paced chip design environments.

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Uvm Verification Engineer jobs near you
Infographic showing various Uvm Verification Engineer job openings in New York as of August 2026, with employment types broken down into 95% Full Time, 2% Part Time, and 3% Contract. Highlights an 86% Physical, 5% Hybrid, and 9% Remote job distribution, with an average salary of $156,030 per year, or $75 per hour.

UVM SYSTEMVERILOG VERIFICATION ENGINEER

Warren, NJ • On-site

Airspan
See more jobs at Airspanexternal

$141K/yr

Full-time

Re-posted 23 days ago

Job description

Airspan Careers
UVM SYSTEMVERILOG VERIFICATION ENGINEER
Location: Warren, New Jersey, Plano, TX or REMOTE U.S.
Company: AirSpan Networks
About AirSpan
AirSpan Networks is a global provider of innovative 4G and 5G network solutions, enabling efficient and cost-effective connectivity for operators, enterprises, and industrial applications. We are looking for a skilled UVM SystemVerilog Verification Engineer to join our dynamic team and contribute to the validation and testing of our cutting-edge communication technologies.
Job Description
As a UVM Verification Engineer, you will be responsible for developing and executing test plans using Universal Verification Methodology (UVM) to validate the functionality, performance, and reliability of AirSpan's ASIC and FPGA designs. You will work closely with design and development teams to ensure compliance with specifications and industry standards.
Key Responsibilities
  • Develop and implement UVM-based verification plans and test strategies for FPGA designs.
  • Perform functional, system-level, and regression testing for digital hardware components.
  • Create test benches, test cases, and automation frameworks in System Verilog.
  • Analyze test results, debug issues, and collaborate with design teams to resolve defects.
  • Ensure compliance with industry standards and customer requirements.
  • Provide documentation and reports on test procedures, results, and defect tracking.
  • Continuously optimize test processes and tools to improve efficiency and accuracy.

Qualifications & Experience
  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related fields.
  • 10 years of experience in UVM-based verification of FPGA systems.
  • Strong understanding of SystemVerilog and Universal Verification Methodology (UVM).
  • Proficiency in scripting languages such as Python or Perl for automation.
  • Experience with simulation tools such as ModelSim or QuestaSim.
  • Experience with C/C++
  • Experience in implementing Bit Accurate Models and debugging DSP designs
  • Familiarity with debugging tools, coverage metrics, and formal verification techniques.
  • Strong problem-solving and analytical skills with attention to detail.
  • Knowledge of O-RAN architecture and protocols for 4G and 5G networks.
  • Ability to work collaboratively in a fast-paced, cross-functional team environment.
  • Design experience a plus.

Preferred Skills
  • Experience in verification of communication protocols.
  • Knowledge of FPGA development and hardware description languages such as VHDL/Verilog.
  • Understanding of hardware/software co-verification techniques.

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