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Verification Engineer Jobs in New York (NOW HIRING)

Airspan

UVM SYSTEMVERILOG VERIFICATION ENGINEER

Warren, NJ · On-site

$141K/yr

Airspan Careers UVM SYSTEMVERILOG VERIFICATION ENGINEER Location: Warren, New Jersey, Plano, TX or REMOTE U.S. Company: AirSpan Networks About AirSpan AirSpan Networks is a global provider of ...

JS Consulting

Senior Verification Engineer

New York, NY · On-site

$114K - $157K/yr

Job Title- Senior Verification Engineer Project Location - On-site 5 days Lake Ronkonkoma NY (Long Island NY) Duration- Fulltime Visa- USC/ GC local candidates only, but might consider someone who is ...

Airspan

FPGA DESIGN ENGINEER

Warren, NJ · On-site

$127K - $176K/yr

You will work closely with system architects, software engineers, and verification engineers to develop high-performance digital hardware solutions. Key Responsibilities: * Design and implement FPGA ...

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Verification Engineer information

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$87.5K

$156K

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How much do verification engineer jobs pay per year?

As of Aug 12, 2026, the average yearly pay for verification engineer in New York is $156,030.00, according to ZipRecruiter salary data. Most workers in this role earn between $148,800.00 and $148,800.00 per year, depending on experience, location, and employer.

What is a verification engineer?

A verification engineer runs tests to ensure products function as expected before they become available to customers. Your job duties as a verification engineer include collaborating with the design team, creating a comprehensive testing process, testing products, providing feedback, and ensuring products are ready on time. The qualifications you need for a career as a verification engineer include a bachelor’s degree in an engineering field, at least two to five years of technical experience, and excellent teamwork skills. You may need Professional Engineer (PE) licensure for some employers.

What are the key skills and qualifications needed to thrive as a verification engineer?

To thrive as a Verification Engineer, you need a strong background in digital design, computer engineering, and verification methodologies, typically supported by a degree in electrical or computer engineering. Familiarity with hardware description languages like Verilog or VHDL, simulation tools (e.g., ModelSim, VCS), and verification frameworks such as UVM is essential. Strong analytical thinking, problem-solving abilities, and effective communication are standout soft skills in this role. These competencies ensure the reliable validation of complex hardware designs, reducing errors and improving product quality throughout the development process.

How does a verification engineer typically collaborate with design and development teams during a project?

Verification Engineers work closely with hardware and software design teams to ensure that products meet technical specifications and function as intended. They participate in regular design reviews, provide feedback on testability, and develop test plans aligned with design goals. Effective communication and collaboration are essential, as Verification Engineers often need to clarify requirements, report bugs, and suggest design improvements. This cross-functional teamwork helps identify issues early, leading to higher-quality products and more efficient project timelines.

What is the difference between Verification Engineer vs Test Engineer?

AspectVerification EngineerTest Engineer
Primary FocusEnsuring design correctness through simulation and formal methodsExecuting tests on hardware or software to validate functionality
Skills & CertificationsKnowledge of verification tools, scripting, HDL languagesTesting methodologies, scripting, hardware/software knowledge
Work EnvironmentDesign teams, simulation labs, verification environmentsTest labs, hardware setups, software testing environments
Industry UsageElectronics, semiconductor, ASIC/IP developmentElectronics, software, embedded systems

Verification Engineers focus on verifying design correctness through simulation and formal methods, while Test Engineers primarily execute tests on hardware or software to validate functionality. Both roles require technical skills and often overlap, but Verification Engineers are more involved in the design validation process, whereas Test Engineers focus on practical testing and validation in real-world environments.

What is a verification engineer?

A Verification Engineer is a professional responsible for ensuring that hardware or software systems meet their design specifications and work as intended. They develop test plans, create test environments, and use various simulation tools to catch bugs and errors before a product goes into production. Verification Engineers play a critical role in the quality assurance process, particularly in industries like semiconductor, electronics, and software development. Their work helps prevent costly design flaws and ensures reliable, high-quality products.
More about Verification Engineer jobs
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Verification Engineer jobs near you
Infographic showing various Verification Engineer job openings in New York as of August 2026, with employment types broken down into 87% Full Time, 7% Part Time, 1% Temporary, and 5% Contract. Highlights an 86% Physical, 5% Hybrid, and 9% Remote job distribution, with an average salary of $156,030 per year, or $75 per hour.

UVM SYSTEMVERILOG VERIFICATION ENGINEER

Airspan

Warren, NJ • On-site

$141K/yr

Full-time

Re-posted 3 days ago

Job description

Airspan Careers
UVM SYSTEMVERILOG VERIFICATION ENGINEER
Location: Warren, New Jersey, Plano, TX or REMOTE U.S.
Company: AirSpan Networks
About AirSpan
AirSpan Networks is a global provider of innovative 4G and 5G network solutions, enabling efficient and cost-effective connectivity for operators, enterprises, and industrial applications. We are looking for a skilled UVM SystemVerilog Verification Engineer to join our dynamic team and contribute to the validation and testing of our cutting-edge communication technologies.
Job Description
As a UVM Verification Engineer, you will be responsible for developing and executing test plans using Universal Verification Methodology (UVM) to validate the functionality, performance, and reliability of AirSpan's ASIC and FPGA designs. You will work closely with design and development teams to ensure compliance with specifications and industry standards.
Key Responsibilities
  • Develop and implement UVM-based verification plans and test strategies for FPGA designs.
  • Perform functional, system-level, and regression testing for digital hardware components.
  • Create test benches, test cases, and automation frameworks in System Verilog.
  • Analyze test results, debug issues, and collaborate with design teams to resolve defects.
  • Ensure compliance with industry standards and customer requirements.
  • Provide documentation and reports on test procedures, results, and defect tracking.
  • Continuously optimize test processes and tools to improve efficiency and accuracy.

Qualifications & Experience
  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related fields.
  • 10 years of experience in UVM-based verification of FPGA systems.
  • Strong understanding of SystemVerilog and Universal Verification Methodology (UVM).
  • Proficiency in scripting languages such as Python or Perl for automation.
  • Experience with simulation tools such as ModelSim or QuestaSim.
  • Experience with C/C++
  • Experience in implementing Bit Accurate Models and debugging DSP designs
  • Familiarity with debugging tools, coverage metrics, and formal verification techniques.
  • Strong problem-solving and analytical skills with attention to detail.
  • Knowledge of O-RAN architecture and protocols for 4G and 5G networks.
  • Ability to work collaboratively in a fast-paced, cross-functional team environment.
  • Design experience a plus.

Preferred Skills
  • Experience in verification of communication protocols.
  • Knowledge of FPGA development and hardware description languages such as VHDL/Verilog.
  • Understanding of hardware/software co-verification techniques.

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