ZipRecruiter

Log In

1

Design Verification Engineer Startup Jobs in New York

Airspan

UVM SYSTEMVERILOG VERIFICATION ENGINEER

Warren, NJ · On-site

$141K/yr

You will work closely with design and development teams to ensure compliance with specifications ... Engineering, or related fields. * 10 years of experience in UVM-based verification of FPGA systems.

JS Consulting

Senior Verification Engineer

New York, NY · On-site

$114K - $157K/yr

Job Title- Senior Verification Engineer Project Location - On-site 5 days Lake Ronkonkoma NY (Long ... Solid understanding of FPGA architecture and digital design. * Hands-on experience with PCIe, 1G ...

Normal Computing

Founding Data Engineer

New York, NY · On-site

$275K - $340K/yr

The Role Our EDA tool accelerates the design and verification of silicon. It integrates with the ... Prior work in a startup or fast-moving research environment where the data strategy was still being ...

Airspan

FPGA DESIGN ENGINEER

Warren, NJ · On-site

$127K - $176K/yr

You will work closely with system architects, software engineers, and verification engineers to develop high-performance digital hardware solutions. Key Responsibilities: * Design and implement FPGA ...

Normal Computing

Hardware Engineer, RTL

New York, NY · On-site

$200K - $285K/yr

The Role As an RTL Design Engineer at Normal, you will design and verify the digital logic at the heart of Normal's thermodynamic hardware. This work sits at the intersection of classical ASIC design ...

OrganOx

Mechanical Design Engineer

Madison, NJ · On-site

$78K - $106K/yr

... design verification and validation • Collaborating with manufacturing and suppliers to ensure ... engineering documentation in accordance with ISO 13485 and other applicable standards • ...

OrganOx

Mechanical Design Engineer

Madison, NJ · On-site

$78K - $106K/yr

... design verification and validation • Collaborating with manufacturing and suppliers to ensure ... engineering documentation in accordance with ISO 13485 and other applicable standards • ...

Antimetal

Design Engineer

New York, NY · On-site

$200K - $300K/yr

We're looking for a design engineer to take ideas from rough sketches to production. You'll play a ... Comfortable in a fast-moving startup environment. You are quick to iterate, test ideas, and push ...

Pace

Design Engineer

Manhattan, NY · On-site

They are seeking a Design Engineer to bridge design and code, shaping the user experience and ... Preferred : • Startup background or founder experience • Have an engineering background ...

EliseAI

Design Engineer

New York, NY · On-site

Startup mindset with a strong sense of ownership, urgency, and pragmatism * Experience in a fast ... visual design best practices * Proficient in Figma * Up-to-date on modern tools and developer ...

next page

Showing results 1-20

All JobsDesign Verification Engineer Startup JobsDesign Verification Engineer Startup Jobs in New York

Design Verification Engineer Startup information

What does a Design Verification Engineer do at a startup?

A Design Verification Engineer at a startup is responsible for ensuring that hardware designs, such as integrated circuits or systems-on-chip, function as intended before they are manufactured. This typically involves developing and running simulations, creating testbenches, writing verification plans, and identifying bugs or mismatches in the design. In a startup environment, Design Verification Engineers often work closely with design, software, and product teams, and may need to wear multiple hats due to limited resources. Their work is crucial in reducing costly errors and speeding up the development cycle, helping the company deliver reliable products to market quickly.

What is the difference between Design Verification Engineer Startup vs Design Verification Engineer Large Corporation?

AspectDesign Verification Engineer StartupDesign Verification Engineer Large Corporation
CredentialsBachelor's or Master's in Electrical Engineering, Computer Engineering, or related fields; certifications like Certified Verification Engineer are commonSame as startup; often similar certifications and educational background
Work EnvironmentAgile, fast-paced, collaborative teams with flexible processesStructured, process-driven, with formal verification methodologies and documentation
Employer & Industry UsageStartups in semiconductor, electronics, or tech sectors; emphasis on innovationLarge tech, semiconductor, or electronics companies with established verification teams
Search & Comparison IntentUnderstanding role differences in startup vs large company

Both roles require similar technical skills and educational backgrounds. The main differences lie in work environment and processes, with startups being more flexible and fast-paced, while large corporations follow formal verification procedures. Candidates should consider their preferred work style when comparing these roles.

What unique challenges might a Design Verification Engineer face when working at a startup compared to a larger company?

At a startup, Design Verification Engineers often work with smaller teams and less established processes, which means you'll likely take on a broader range of responsibilities—from testbench development to hands-on debugging and even influencing verification methodologies. The fast-paced environment can present challenges such as tighter deadlines, limited resources, and rapidly changing project scopes. However, this setting also allows for closer collaboration with design, software, and product teams, fostering a greater sense of ownership and quicker decision-making. Your contributions are highly visible, and there's significant potential for accelerated career growth as the company scales.

What are the key skills and qualifications needed to thrive as a Design Verification Engineer at a startup, and why are they important?

To thrive as a Design Verification Engineer at a startup, you need a strong background in digital design, verification methodologies, and a relevant degree in electrical engineering or computer science. Familiarity with tools like SystemVerilog, UVM, simulation environments, and version control systems is typically required, along with experience in scripting languages. Strong problem-solving abilities, adaptability, and effective communication are crucial soft skills, especially in fast-paced startup environments. These skills ensure efficient bug detection, robust product development, and successful collaboration within small, agile teams.
What are popular job titles related to Design Verification Engineer Startup jobs in New York? For Design Verification Engineer Startup jobs in New York, the most frequently searched job titles are:
What job categories do people searching Design Verification Engineer Startup jobs in New York look for? The top searched job categories for Design Verification Engineer Startup jobs in New York are:
What cities in New York are hiring for Design Verification Engineer Startup jobs? Cities in New York with the most Design Verification Engineer Startup job openings:
Design Verification Engineer Startup jobs near you

Design Verification Engineer

Normal Computing

New York, NY • On-site

$140K - $180K/yr

Full-time

Posted 21 days ago

Job description

About Normal Computing
Normal Computing builds silicon that turns thermal noise from an obstacle into a computational resource. Conventional chips spend most of their energy forcing determinism onto physics; ours compute with it. Stochastic, in-memory, asynchronous: the result is 10-100× more AI inference per dollar, per watt.
We co-design the full stack: AI-native EDA systems in production with the world's largest semiconductor companies, and the advanced ASICs they make possible. Backed by $85M+ from the world's leading deep-tech investors and built by scientists, engineers, and operators from the labs that built modern computing.
Normal works as one team across New York, Silicon Valley, London, Copenhagen, and Seoul. We hire people who want the hardest version of their craft, across every discipline, at every seniority.
The Role
As a Design Verification Engineer at Normal, you will verify our own physics-inspired ASICs on the road to tapeout, and set the quality bar for what our AI learns: reviewing generated verification collateral and shaping the standards our models train against. From time to time, you may also be tapped to support a customer deployment alongside our forward-deployed team, where your verification credibility helps our AI platform land inside real DV flows. The through-line is your DV expertise, applied to silicon that computes differently than anything you've verified before, and to the AI that is changing how verification gets done. This is a seat for a verification engineer who wants their craft to compound rather than repeat.
What You Will Own
  • Thermodynamic ASIC Verification: Own design verification for Normal's internal silicon: testbench environments, assertions, and coverage from design documents through functional coverage and closure, supporting the program to tapeout.
  • AI Product Refinement: Review AI-generated verification collateral to shape product strategy and tool usability in collaboration with the ML and product teams.
  • Data Quality Bar: Set the quality standard for verification training data: define rubrics, curate golden examples, and partner with our Data team, who own the pipelines, so our models learn from verification artifacts a real DV engineer would sign off on.
  • Deployment Support: When needed, support customer engagements alongside our forward-deployed team: validating AI-generated collateral against real customer specifications and lending DV credibility to deployments.
  • Tooling: Set up and evaluate EDA tools, ensuring usability and effective deployment on shared computing resources internally and in customer environments.

What Makes You a Great Fit
  • 5+ years of experience in digital verification at a major semiconductor or EDA tool company
  • Advanced proficiency in SystemVerilog, UVM methodology, and EDA verification tools (vManager, Xcelium, Jasper), with strong Python or Perl scripting
  • Proven expertise in end-to-end design verification, including test plan creation, stimulus generation, and feature extraction
  • Willingness to occasionally support customer-facing deployment work, including some travel
  • Excellent written and spoken communication skills: you can hold the room with a customer's verification lead as credibly as you hold a debug session

Bonus Points
  • Experience in a customer-facing, field-application, or forward-deployed engineering role at a semiconductor or EDA company
  • Hands-on use of LLMs or agentic tools in verification workflows
  • Exposure to analog, mixed-signal, or unconventional compute verification

Equal Employment Opportunity Statement
Normal Computing is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other legally protected status.
Accessibility Accommodations
Normal Computing is committed to providing reasonable accommodations to individuals with disabilities. If you need assistance or an accommodation due to a disability, please let us know at accommodations@normalcomputing.com.
Privacy Notice
By submitting your application, you agree that Normal Computing may collect, use, and store your personal information for employment-related purposes in accordance with our Privacy Policy.

Apply