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Internship Asic Rtl Design Engineer Jobs in New York

Jane Street

ASIC Engineer

New York, NY

$181K/yr

Have 4+ years practical experience in RTL design and verification * Experienced in ASIC design ... Interested in using software engineering techniques to improve the hardware design process, and ...

Jane Street

ASIC Engineer

New York, NY · On-site

$181K/yr

Have 4+ years practical experience in RTL design and verification * Experienced in ASIC design ... Interested in using software engineering techniques to improve the hardware design process, and ...

Normal Computing

Hardware Engineer, RTL

New York, NY · On-site

$200K - $285K/yr

The Role As an RTL Design Engineer at Normal, you will design and verify the digital logic at the ... This work sits at the intersection of classical ASIC design, novel computing architectures, and a ...

Jane Street

Hardware Engineer (FPGA/ASIC)

New York, NY · On-site

We expect interns to build hardware applications from concept to a working design; your projects ... both RTL design and testing/integration. If you'd like to learn more, you can read about our ...

Jane Street

ASIC Physical Design Engineer

New York, NY · On-site

$148K - $153K/yr

About the Position We are looking to hire an ASIC Physical Design Engineer to help us design, test ... You should be comfortable owning a PD flow end-to-end, but also able to read and write RTL and ...

Jane Street

ASIC Physical Design Engineer

New York, NY

$148K - $153K/yr

About the Position We are looking to hire an ASIC Physical Design Engineer to help us design, test ... You should be comfortable owning a PD flow end-to-end, but also able to read and write RTL and ...

Normal Computing

Hardware Engineer, FPGA

New York, NY · On-site

$200K - $280K/yr

As our FPGA Design Engineer, you will own the bridge between RTL and physical silicon: bringing our physics-inspired ASIC designs to life on FPGA platforms for pre-silicon validation and early ...

Ciena Corporation

THW Client Co-op

New York, NY · On-site

$27 - $37.50/hr

RTL design and verification of digital blocks, cores, and subsystems for ASIC products and FPGA ... Engineering - Previous experience with ASIC or FPGA development, as well as knowledge of and ...

Jane Street

Hardware Engineer

New York, NY · On-site

$135K - $178K/yr

We use Hardcaml, an OCaml library for succinctly describing hardware in RTL. Hardcaml is tightly ... In this role, you'll work on the ground-up design and implementation of new FPGA or ASIC ...

New

Jane Street

Hardware Engineer

New York, NY

$135K - $178K/yr

We use Hardcaml, an OCaml library for succinctly describing hardware in RTL. Hardcaml is tightly ... In this role, you'll work on the ground-up design and implementation of new FPGA or ASIC ...

New

QCi

FPGA Design Engineer

Hoboken, NJ · On-site

$134K - $185K/yr

FPGA Design Engineer Location: Hoboken, NJ Division : Technology Department: Engineering Reports to ... Develop RTL code for use within multiple projects. Analyze and enhance efficiency, scalability, and ...

Quantum Computing Inc.

FPGA Design Engineer

Hoboken, NJ · On-site

$134K - $185K/yr

FPGA Design Engineer Location: Hoboken, NJ Division : Technology Department: Engineering Reports to ... Develop RTL code for use within multiple projects. Analyze and enhance efficiency, scalability, and ...

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Internship Asic Rtl Design Engineer information

What types of projects and responsibilities can an intern expect as an ASIC RTL Design Engineer?

As an ASIC RTL Design Engineering intern, you'll typically work on tasks such as writing and verifying RTL code using languages like Verilog or VHDL, assisting with simulation and debugging, and collaborating closely with senior engineers on real design blocks. Interns often participate in design reviews, update documentation, and may get hands-on experience with synthesis and timing analysis tools. This role is highly collaborative and provides exposure to the complete ASIC development cycle, making it an excellent opportunity to build foundational skills and gain insight into industry-standard methodologies.

What are the key skills and qualifications needed to thrive as an Internship ASIC RTL Design Engineer, and why are they important?

To thrive as an Internship ASIC RTL Design Engineer, you need a solid understanding of digital logic design, computer architecture, and proficiency in HDL languages like Verilog or VHDL, typically supported by coursework in electrical or computer engineering. Familiarity with industry-standard EDA tools such as Synopsys, Cadence, or Mentor Graphics, and simulation environments is highly valuable. Strong analytical thinking, attention to detail, and effective communication skills help interns collaborate with teams and learn quickly in a fast-paced environment. These skills and qualities are essential for contributing to complex chip design projects and ensuring accuracy and efficiency in RTL development.

What is an Internship ASIC RTL Design Engineer?

An Internship ASIC RTL (Register Transfer Level) Design Engineer is a student or recent graduate who assists in designing and developing digital integrated circuits (ICs) using hardware description languages like Verilog or VHDL. They work under the guidance of senior engineers to create, simulate, and verify RTL code for ASIC (Application Specific Integrated Circuit) projects. The role provides hands-on experience with the chip design process, including synthesis, timing analysis, and verification. Interns gain valuable exposure to industry-standard tools and methodologies, helping them prepare for a full-time engineering career.

What is the difference between Internship Asic Rtl Design Engineer vs Asic Verification Engineer?

AspectInternship Asic Rtl Design EngineerAsic Verification Engineer
CredentialsTypically pursuing or recently completed a degree in Electrical Engineering or Computer EngineeringSimilar educational background, often with additional coursework in verification methodologies
Work EnvironmentInternship setting, supervised, focused on learning and assisting in RTL design tasksFull-time role, focused on testing and verifying RTL designs
Industry UsageUsed in semiconductor and chip design companies during early career stagesCommon in companies developing complex integrated circuits and chips

The Internship Asic Rtl Design Engineer focuses on assisting in RTL design tasks during an internship, emphasizing learning and support. In contrast, the Asic Verification Engineer is responsible for verifying RTL designs to ensure functionality. Both roles require similar educational backgrounds but differ in responsibilities and work environment, with verification roles being more advanced and permanent.

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Internship Asic Rtl Design Engineer jobs near you
Principal Digital Design Engineer (ASIC)

Principal Digital Design Engineer (ASIC)

Analog Devices

Somerset, NJ • On-site

$143K/yr

Full-time

Medical, Dental, Vision, Retirement, PTO

Posted 4 days ago

Analog Devices rating

8.5

Company rating: 8.5 out of 10

Based on 17 frontline employees who took The Breakroom Quiz

31st of 155 rated electronics manufacturers

Job description

About Analog Devices
Analog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.
Principal Digital Design Engineer
About the Role
As a Principal Digital Design Engineer, you will drive technical strategy and innovation for complex digital systems, including System on Chips (SoCs). You'll define product and technology roadmaps, lead ASIC architecture for mission-critical projects, and serve as a technical authority within the organization. This position requires exceptional expertise across multiple domains and the ability to influence business direction while mentoring and developing technical talent.
Key Responsibilities
  • Develop and maintain system-level models (e.g., in SystemVerilog, or MATLAB) to analyze architectural trade-offs, verify system behavior, and inform hardware/software partitioning.
  • Own the architecture, micro-architecture, and RTL design of complex digital blocks and/or subsystems (such as signal processing functions, control, or processor subsystems) for mixed signal ICs.
  • Collaborate closely with multi location teams such as system architects, analog designers, DV, physical design, product engineering, applications, and firmware teams to during architecture, design, evaluation, and release phases.
  • Lead design reviews, participate in specification, and ensure alignment with broader project goals.
  • Perform RTL coding (Verilog and SystemVerilog), synthesis, and lint/CDC analysis; drive designs to timing closure and area/power targets.
  • Develop and execute verification plans in collaboration with DV, including functional coverage and support for simulation/debug.
  • Analyze and resolve design, timing, and functional issues across the full digital development flow.
  • Contribute to top-level integration, including interface definition, constraint development, and support for physical implementation for functional and DFT modes.
  • Mentor and guide junior engineers, sharing expertise and promoting best practices.
  • Author and maintain clear documentation, user guides, and design collateral.
  • Stay current with industry trends and identify opportunities for process or technology improvement.
  • Perform silicon lab evaluation and debug.
  • Use Python applications to develop tests on evaluation platforms.

Must Have Skills
  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
  • 10+ years of experience in digital design for ASIC/SoC, with track record of successful tapeouts.
  • Strong understanding of ASIC Design flow
  • Expertise in RTL design (SystemVerilog), logic synthesis, and digital verification methodologies with Cadence tools.
  • Experience with modeling and scripting (Matlab, TCL, Python) for design automation.
  • Strong understanding of digital design flows, timing analysis, and constraints.
  • Experience collaborating across functions (DV, PD, systems, analog/mixed-signal).
  • Excellent communication and documentation skills.
  • Demonstrated ability to lead technical projects or major design subsystems.
  • Strong understanding of business context and ability to align technical strategy with business goals

Preferred Qualifications:
  • Experience with high-speed interfaces, high speed signal processing, and low-power design.
  • Familiarity with UVM or similar verification frameworks.
  • Prior mentorship or technical leadership experience.

Preferred Education and Experience
  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or equivalent experience
  • 12+ years of relevant experience in digital design engineering

Why You'll Love Working Here
At Analog Devices, you'll be part of a collaborative and innovative team that's shaping the future of technology. We offer a supportive environment focused on professional growth, competitive compensation and benefits, work-life balance, and the opportunity to work on cutting-edge projects that make a real impact on the world.
Your expertise will shape the future of technology, and you'll be supported by a culture that values continuous advancement and professional growth. Join us and help create the technologies that bridge the physical and digital worlds, making a tangible difference in how people live, work, and connect.
#LI-PG1
For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position - except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) - may have to go through an export licensing review process.
Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.
EEO is the Law: Notice of Applicant Rights Under the Law.
Job Req Type: Experienced
Required Travel: Yes, 10% of the time
Shift Type: 1st Shift/Days
The expected wage range for a new hire into this position is $159,638 to $239,457.
  • Actual wage offered may vary depending on work location, experience, education, training, external market data, internal pay equity, or other bona fide factors.
  • This position qualifies for a discretionary performance-based bonus which is based on personal and company factors.
  • This position includes medical, vision and dental coverage, 401k, paid vacation, holidays, and sick time, and other benefits.

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About Analog Devices

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Analog Devices (NASDAQ: ADI) designs and manufactures semiconductor products and solutions. We enable our customers to interpret the world around us by intelligently bridging the physical and digital worlds with unmatched technologies that sense, measure and connect.

Industry

Electrical equipment, appliance, and component manufacturing

Company size

5,001 - 10,000 Employees

Headquarters location

Norwood, MA, US

Year founded

1965

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