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New Grad Asic Design Verification Engineer Jobs in New York

Normal Computing

Design Verification Engineer

New York, NY · On-site

$200K - $400K/yr

Normal works as one team across New York, Silicon Valley, London, Copenhagen, and Seoul. We hire ... Thermodynamic ASIC Verification: Own design verification for Normal's internal silicon: testbench ...

Jane Street

ASIC Engineer

Manhattan, NY · On-site

$183K/yr

... new things as a result. About You ... Have 4+ years practical experience in RTL design and verification * Experienced in ASIC design ...

Jane Street

ASIC Engineer

New York, NY · On-site

$181K/yr

... new things as a result. About You ... Have 4+ years practical experience in RTL design and verification * Experienced in ASIC design ...

Jane Street

ASIC Engineer

New York, NY · On-site

$181K/yr

... new things as a result. About You ... Have 4+ years practical experience in RTL design and verification * Experienced in ASIC design ...

Cisco

Design Verification Engineer - Acacia (Onsite)

Holmdel, NJ · On-site

$154K - $225K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

... optical packaging, ASIC development, and the operations teams to deliver leading edge, high ... New product introduction - work closely with RF, silicon photonics, DSP, and module design teams to ...

Cisco

Design Verification Engineer - Acacia (Onsite)

Holmdel, NJ

$154K - $225K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

... optical packaging, ASIC development, and the operations teams to deliver leading edge, high ... New product introduction - work closely with RF, silicon photonics, DSP, and module design teams to ...

Ciena Corporation

THW Client Co-op

New York, NY · On-site

$27 - $37.50/hr

  • PTO

As a successful candidate, you will be working within the ASIC IP team with other design and verification engineers, performing digital ASIC design and verification of the Client sub-systems and ...

Normal Computing

Hardware Engineer, RTL

New York, NY · On-site

$200K - $400K/yr

Normal works as one team across New York, Silicon Valley, London, Copenhagen, and Seoul. We hire ... ASIC or SoC design Bonus Points * Experience at an AI chip company where design and verification ...

Ciena

Principal Digital Verification Engineer

Manhattan, NY · On-site

$147K - $234K/yr

  • Medical

  • Dental

  • Vision

  • Retirement

  • PTO

... design engineers, verification engineers and architects, in our Rochester NY office. Your role as ... As an ASIC verification Prime, you would be responsible for all aspects of the verification of the ...

Collabera Digital

Verification Engineer

New York, NY · On-site

$180K - $230K/yr

  • Medical

  • Dental

  • Vision

  • Retirement

  • PTO

The Electronics Verification Engineer is responsible for validating and qualifying electronic ... and design-for-test concepts. Location: New York Salary Range: The salary for this position is ...

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All JobsNew Grad Asic Design Verification Engineer JobsNew Grad Asic Design Verification Engineer Jobs in New York

New Grad Asic Design Verification Engineer information

What does a new grad ASIC design verification engineer do?

A New Grad ASIC Design Verification Engineer is responsible for testing and validating the design of Application-Specific Integrated Circuits (ASICs) to ensure they meet functional and performance specifications. They typically create testbenches, develop verification plans, write test cases using hardware description languages like SystemVerilog, and debug issues found during simulations. This role is crucial for catching design flaws before manufacturing, working closely with design engineers and using both manual and automated verification methods. As a new graduate, you will learn industry-standard verification methodologies and tools while contributing to the success of the silicon development process.

What are the key skills and qualifications needed to thrive as a new grad ASIC design verification engineer?

To thrive as a New Grad ASIC Design Verification Engineer, you need a solid understanding of digital design principles, hardware description languages (such as Verilog or VHDL), and a relevant degree in electrical or computer engineering. Familiarity with industry-standard verification tools and environments like SystemVerilog, UVM, and simulation/debugging platforms is typically required. Strong analytical thinking, attention to detail, and effective teamwork skills help you excel in diagnosing issues and collaborating with design teams. These skills and qualities ensure robust verification processes that lead to functional, reliable ASIC products.

What are some common challenges new graduates face when starting as an ASIC design verification engineer, and how can they overcome them?

New grad ASIC Design Verification Engineers often encounter challenges such as understanding complex verification environments, learning industry-standard tools and methodologies like UVM, and effectively debugging hardware designs. To overcome these, it's helpful to actively seek mentorship from experienced team members, participate in code reviews, and utilize available documentation and training resources. Collaborating closely with designers and verification leads, asking questions, and consistently practicing hands-on simulations can accelerate learning and build confidence in tackling verification tasks.

What is the difference between New Grad Asic Design Verification Engineer vs New Grad Digital Design Engineer?

AspectNew Grad Asic Design Verification EngineerNew Grad Digital Design Engineer
Required SkillsHardware verification, simulation, scripting, HDL knowledgeDigital circuit design, HDL coding, logic design
Work EnvironmentVerification labs, simulation tools, hardware testingDesign teams, FPGA/ASIC development, coding
Industry UsagePrimarily in semiconductor and chip companiesBroadly in electronics, semiconductor, and tech firms

While both roles require HDL knowledge and work in semiconductor environments, the New Grad Asic Design Verification Engineer focuses on verifying and testing ASIC designs, whereas the New Grad Digital Design Engineer is involved in designing digital circuits. Both roles are essential in chip development but differ in their primary responsibilities and skill emphasis.

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For New Grad Asic Design Verification Engineer jobs in New York, the most frequently searched job titles are:

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New Grad Asic Design Verification Engineer jobs near you
Infographic showing various New Grad Asic Design Verification Engineer job openings in New York as of August 2026, with employment types broken down into 86% Full Time, 10% Part Time, and 4% Contract. Highlights an 85% Physical, 4% Hybrid, and 11% Remote job distribution.

Design Verification Engineer

Normal Computing

New York, NY • On-site

$200K - $400K/yr

Full-time

Re-posted 15 days ago

Job description

About Normal Computing
Normal Computing builds silicon that turns thermal noise from an obstacle into a computational resource. Conventional chips spend most of their energy forcing determinism onto physics; ours compute with it. Stochastic, in-memory, asynchronous: the result is 10-100× more AI inference per dollar, per watt.
We co-design the full stack: AI-native EDA systems in production with the world's largest semiconductor companies, and the advanced ASICs they make possible. Backed by $85M+ from the world's leading deep-tech investors and built by scientists, engineers, and operators from the labs that built modern computing.
Normal works as one team across New York, Silicon Valley, London, Copenhagen, and Seoul. We hire people who want the hardest version of their craft, across every discipline, at every seniority.
The Role
As a Design Verification Engineer at Normal, you will verify our own physics-inspired ASICs on the road to tapeout, and set the quality bar for what our AI learns: reviewing generated verification collateral and shaping the standards our models train against. From time to time, you may also be tapped to support a customer deployment alongside our forward-deployed team, where your verification credibility helps our AI platform land inside real DV flows. The through-line is your DV expertise, applied to silicon that computes differently than anything you've verified before, and to the AI that is changing how verification gets done. This is a seat for a verification engineer who wants their craft to compound rather than repeat.
What You Will Own
  • Thermodynamic ASIC Verification: Own design verification for Normal's internal silicon: testbench environments, assertions, and coverage from design documents through functional coverage and closure, supporting the program to tapeout.
  • AI Product Refinement: Review AI-generated verification collateral to shape product strategy and tool usability in collaboration with the ML and product teams.
  • Data Quality Bar: Set the quality standard for verification training data: define rubrics, curate golden examples, and partner with our Data team, who own the pipelines, so our models learn from verification artifacts a real DV engineer would sign off on.
  • Deployment Support: When needed, support customer engagements alongside our forward-deployed team: validating AI-generated collateral against real customer specifications and lending DV credibility to deployments.
  • Tooling: Set up and evaluate EDA tools, ensuring usability and effective deployment on shared computing resources internally and in customer environments.

What Makes You a Great Fit
  • 5+ years of experience in digital verification at a major semiconductor or EDA tool company
  • Advanced proficiency in SystemVerilog, UVM methodology, and EDA verification tools (vManager, Xcelium, Jasper), with strong Python or Perl scripting
  • Proven expertise in end-to-end design verification, including test plan creation, stimulus generation, and feature extraction
  • Willingness to occasionally support customer-facing deployment work, including some travel
  • Excellent written and spoken communication skills: you can hold the room with a customer's verification lead as credibly as you hold a debug session

Bonus Points
  • Experience in a customer-facing, field-application, or forward-deployed engineering role at a semiconductor or EDA company
  • Hands-on use of LLMs or agentic tools in verification workflows
  • Exposure to analog, mixed-signal, or unconventional compute verification

Equal Employment Opportunity Statement
Normal Computing is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other legally protected status.
Accessibility Accommodations
Normal Computing is committed to providing reasonable accommodations to individuals with disabilities. If you need assistance or an accommodation due to a disability, please let us know at accommodations@normalcomputing.com.
Privacy Notice
By submitting your application, you agree that Normal Computing may collect, use, and store your personal information for employment-related purposes in accordance with our Privacy Policy.

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