Evaluate digital chip design workflows to enhance AI model training and evaluation . * Design and verify RTL components using Verilog/SystemVerilog . * Collaborate with architecture, verification ...
Quick apply
Evaluate digital chip design workflows to enhance AI model training and evaluation . * Design and verify RTL components using Verilog/SystemVerilog . * Collaborate with architecture, verification ...
Hardware Engineer, RTL
New York, NY · On-site
$200K - $285K/yr
Experience at an AI chip company where design and verification were tightly coupled * Open-source RTL contributions to projects like Chipyard, OpenTitan, or CVA6 * Familiarity with RISC-V or other ...
Hardware Engineer, RTL
New York, NY · On-site
$200K - $285K/yr
Experience at an AI chip company where design and verification were tightly coupled * Open-source RTL contributions to projects like Chipyard, OpenTitan, or CVA6 * Familiarity with RISC-V or other ...
Remote | ASIC/SoC Hardware Design & Verification Engineer - $65-$95/hour
Manhattan, NY · On-site +1
$65 - $95/hr
Create realistic tasks grounded in actual chip design and verification work * Evaluate how AI systems approach complex RTL, debugging, and hardware-reasoning problems * Collaborate with engineers ...
Remote | ASIC/SoC Hardware Design & Verification Engineer - $65-$95/hour
Manhattan, NY · On-site +1
$65 - $95/hr
Create realistic tasks grounded in actual chip design and verification work * Evaluate how AI systems approach complex RTL, debugging, and hardware-reasoning problems * Collaborate with engineers ...
ASIC Physical Design Engineer
New York, NY · On-site
$148K - $153K/yr
... chip designers. You should be comfortable owning a PD flow end-to-end, but also able to read and write RTL and reason about design decisions that cross the front-end/back-end boundary. If you've ...
ASIC Physical Design Engineer
New York, NY · On-site
$148K - $153K/yr
... chip designers. You should be comfortable owning a PD flow end-to-end, but also able to read and write RTL and reason about design decisions that cross the front-end/back-end boundary. If you've ...
ASIC Physical Design Engineer
New York, NY · On-site
$148K - $153K/yr
... chip designers. You should be comfortable owning a PD flow end-to-end, but also able to read and write RTL and reason about design decisions that cross the front-end/back-end boundary. If you've ...
ASIC Physical Design Engineer
New York, NY · On-site
$148K - $153K/yr
... chip designers. You should be comfortable owning a PD flow end-to-end, but also able to read and write RTL and reason about design decisions that cross the front-end/back-end boundary. If you've ...
Senior VLSI CAD Software Engineer
$134K - $176K/yr
... AI to define the next era of computing. An era in which our GPU acts as the brains of computers ... Design, development, review, test, and support of high-capacity and high-performance chip design ...
Senior VLSI CAD Software Engineer
$134K - $176K/yr
... AI to define the next era of computing. An era in which our GPU acts as the brains of computers ... Design, development, review, test, and support of high-capacity and high-performance chip design ...
... AI) computational structures intended for chip-scale implementation. This role focuses on ... design robustness. Optimize photonic device structures for performance, scalability, and ...
... AI) computational structures intended for chip-scale implementation. This role focuses on ... design robustness. Optimize photonic device structures for performance, scalability, and ...
... AI) computational structures intended for chip-scale implementation. This role focuses on ... design robustness. Optimize photonic device structures for performance, scalability, and ...
... AI) computational structures intended for chip-scale implementation. This role focuses on ... design robustness. Optimize photonic device structures for performance, scalability, and ...
AI Engineer
New York, NY · On-site
$200K - $300K/yr
The Role As an AI Engineer at Normal, you will build production systems that understand large technical documents, like chip design specifications, and turn them into code. You'll ship real ...
AI Engineer
New York, NY · On-site
$200K - $300K/yr
The Role As an AI Engineer at Normal, you will build production systems that understand large technical documents, like chip design specifications, and turn them into code. You'll ship real ...
Hardware Engineer, Architect
New York, NY · On-site
$234K - $298K/yr
We co-design the full stack: AI-native EDA systems in production with the world's largest ... Move between algorithm-level workload behavior, memory hierarchy, on-chip interconnect, and ...
Hardware Engineer, Architect
New York, NY · On-site
$234K - $298K/yr
We co-design the full stack: AI-native EDA systems in production with the world's largest ... Move between algorithm-level workload behavior, memory hierarchy, on-chip interconnect, and ...
Vice President
New York, NY · On-site
... chip design services at scale. Focused exclusively on microchip design, embedded solutions and AI ... RTL design through physical implementation, verification, and tape-out management. Our clients span ...
Vice President
New York, NY · On-site
... chip design services at scale. Focused exclusively on microchip design, embedded solutions and AI ... RTL design through physical implementation, verification, and tape-out management. Our clients span ...
... chip design services at scale. Focused exclusively on microchip design, embedded solutions and AI ... RTL design through physical implementation, verification, and tape-out management. Our clients span ...
... chip design services at scale. Focused exclusively on microchip design, embedded solutions and AI ... RTL design through physical implementation, verification, and tape-out management. Our clients span ...
... chip design services at scale. Focused exclusively on microchip design, embedded solutions and AI ... RTL design through physical implementation, verification, and tape-out management. Our clients span ...
... chip design services at scale. Focused exclusively on microchip design, embedded solutions and AI ... RTL design through physical implementation, verification, and tape-out management. Our clients span ...
AI-native electronic design automation (EDA) and chip design * Any other discipline where physical or biological priors in AI can bring breakthrough scale and generalization A research scientist in ...
AI-native electronic design automation (EDA) and chip design * Any other discipline where physical or biological priors in AI can bring breakthrough scale and generalization A research scientist in ...
Hardware Engineer
New York, NY · On-site
$135K - $178K/yr
Strong skills in RTL design (SystemVerilog) and verification. Strong working knowledge of Xilinx design flows (synthesis, place & route, timing analysis). Knowledge of TCP/IP stack and on-chip ...
Hardware Engineer
New York, NY · On-site
$135K - $178K/yr
Strong skills in RTL design (SystemVerilog) and verification. Strong working knowledge of Xilinx design flows (synthesis, place & route, timing analysis). Knowledge of TCP/IP stack and on-chip ...
Hardware Engineer
New York, NY · On-site
$135K - $178K/yr
... RTL design (SystemVerilog) and verification. • Strong working knowledge of Xilinx design flows (synthesis, place & route, timing analysis). • Knowledge of TCP/IP stack and on-chip networking ...
Hardware Engineer
New York, NY · On-site
$135K - $178K/yr
... RTL design (SystemVerilog) and verification. • Strong working knowledge of Xilinx design flows (synthesis, place & route, timing analysis). • Knowledge of TCP/IP stack and on-chip networking ...
Principal Digital Design Engineer (ASIC)
Somerset, NJ · On-site
$143K/yr
ADI combines analog, digital, AI, and software technologies into solutions that combat climate ... Own the architecture, micro-architecture, and RTL design of complex digital blocks and/or ...
Principal Digital Design Engineer (ASIC)
Somerset, NJ · On-site
$143K/yr
ADI combines analog, digital, AI, and software technologies into solutions that combat climate ... Own the architecture, micro-architecture, and RTL design of complex digital blocks and/or ...
ADI combines analog, digital, AI, and software technologies into solutions that combat climate ... Own the architecture, micro-architecture, and RTL design of complex digital blocks and/or ...
ADI combines analog, digital, AI, and software technologies into solutions that combat climate ... Own the architecture, micro-architecture, and RTL design of complex digital blocks and/or ...
Hardware Engineer, FPGA
New York, NY · On-site
$200K - $280K/yr
We co-design the full stack: AI-native EDA systems in production with the world's largest ... RTL Implementation : Adapt and implement complex ASIC RTL onto FPGA targets, including multi-clock ...
Hardware Engineer, FPGA
New York, NY · On-site
$200K - $280K/yr
We co-design the full stack: AI-native EDA systems in production with the world's largest ... RTL Implementation : Adapt and implement complex ASIC RTL onto FPGA targets, including multi-clock ...
FPGA DESIGN ENGINEER
Warren, NJ · On-site
$127K - $176K/yr
Develop RTL designs in Verilog/System Verilog , ensuring efficient and high-performance ... Preferred Skills: * Experience with FPGA-based acceleration for AI/ML applications
FPGA DESIGN ENGINEER
Warren, NJ · On-site
$127K - $176K/yr
Develop RTL designs in Verilog/System Verilog , ensuring efficient and high-performance ... Preferred Skills: * Experience with FPGA-based acceleration for AI/ML applications
Ai Chip Design Rtl information
What is a $900000 AI job?
A $900,000 AI job typically refers to a high-level position in artificial intelligence, such as senior AI researcher, machine learning engineer, or AI architect, often requiring advanced skills in deep learning, neural networks, and hardware design like RTL for AI chips. Such roles usually involve leadership, extensive experience, and may include stock options or bonuses, with compensation reflecting expertise and impact on AI hardware development.
What is the difference between Ai Chip Design Rtl vs Ai Chip Verification Engineer?
| Aspect | Ai Chip Design Rtl | Ai Chip Verification Engineer |
|---|---|---|
| Primary Focus | Developing and implementing Register Transfer Level (RTL) code for AI chips | Verifying and validating RTL designs to ensure functionality |
| Skills Required | HDL languages (Verilog/VHDL), digital design, FPGA/ASIC knowledge | Simulation, testbench creation, debugging, scripting skills |
| Work Environment | Design teams, hardware development labs, EDA tools | Verification teams, simulation environments, test setups |
| Certifications | Hardware design certifications, FPGA/ASIC training | Verification methodologies, UVM, SystemVerilog certifications |
While Ai Chip Design Rtl focuses on creating the hardware description code for AI chips, Ai Chip Verification Engineer ensures that the RTL design functions correctly through rigorous testing. Both roles require knowledge of HDL languages and work closely within hardware development teams, but their core responsibilities differ—design versus verification.
Will AI replace RTL designers?
AI chip design RTL (Register Transfer Level) development involves creating hardware descriptions that require expert knowledge of digital logic and hardware architecture. While AI tools can assist in automating certain tasks like code generation and verification, they are unlikely to fully replace RTL designers, as human expertise is essential for complex decision-making, optimization, and ensuring design correctness. RTL designers will continue to play a critical role in the chip design process, often working alongside AI-assisted tools to improve efficiency and innovation.
What are some common challenges faced by AI Chip Design RTL engineers during the verification process?
AI Chip Design RTL engineers often encounter challenges in ensuring their designs meet complex functional and performance requirements, especially given the rapid pace of AI hardware advancements. Verification can be particularly demanding due to the need to simulate and test intricate AI workloads, manage large datasets, and debug subtle timing or logic errors. Collaboration with verification teams, system architects, and software engineers is essential to address these issues efficiently and to ensure seamless integration of the RTL code into the broader chip design. Staying up-to-date with the latest verification tools and methodologies is also crucial for success in this role.
Which 3 jobs will survive AI?
AI Chip Design RTL professionals are likely to continue in demand due to the specialized technical skills required for hardware description languages like Verilog and VHDL, which are less easily automated. Jobs involving complex problem-solving, system integration, and hardware-software interface design, such as hardware engineers, system architects, and verification engineers, are also expected to persist. These roles require domain expertise and critical thinking that complement AI automation capabilities.
What are AI Chip Design RTL engineers?
AI Chip Design RTL (Register Transfer Level) engineers are specialists who design the digital logic for chips used in artificial intelligence applications. They use hardware description languages like Verilog or VHDL to create and validate the architecture and functionality of these chips before they are manufactured. Their work ensures that AI processors are efficient, high-performing, and meet the requirements of modern AI workloads. RTL engineers collaborate closely with verification, software, and hardware teams to optimize chip performance and power consumption.
What is the salary of RTL design?
The salary for an RTL (Register Transfer Level) design engineer typically ranges from $80,000 to $150,000 annually, depending on experience, location, and company size. Entry-level positions may start lower, while experienced engineers with specialized skills in hardware description languages like VHDL or Verilog can earn higher salaries.
What are the key skills and qualifications needed to thrive as an AI Chip Design RTL Engineer, and why are they important?
To thrive as an AI Chip Design RTL Engineer, you need a solid background in digital design, computer architecture, and proficiency in Hardware Description Languages (HDLs) like Verilog or VHDL, often supported by a degree in electrical or computer engineering. Experience with simulation tools (e.g., ModelSim, Synopsys), ASIC/FPGA design flows, and relevant certifications are highly valued. Strong problem-solving abilities, attention to detail, and effective teamwork and communication skills help you excel in collaborative and complex design environments. These competencies are crucial for creating efficient, reliable AI hardware that meets performance and power requirements in a fast-evolving field.
What are popular job titles related to Ai Chip Design Rtl jobs in New York? For Ai Chip Design Rtl jobs in New York, the most frequently searched job titles are:
What job categories do people searching Ai Chip Design Rtl jobs in New York look for? The top searched job categories for Ai Chip Design Rtl jobs in New York are:
What cities in New York are hiring for Ai Chip Design Rtl jobs? Cities in New York with the most Ai Chip Design Rtl job openings:
$175/hr
Full-time
Posted 8 hours ago
Job description
About the job
Mercor connects elite creative and technical talent with leading AI research labs. Headquartered in San Francisco, our investors include Benchmark, General Catalyst, Peter Thiel, Adam D'Angelo, Larry Summers, and Jack Dorsey.
Position: RTL Design Engineers
Type: Contract
Compensation: $100–$175/hour
Location: Remote
Duration: 3+ months
Commitment: 40 hours/week
Role Responsibilities
- Evaluate digital chip design workflows to enhance AI model training and evaluation.
- Design and verify RTL components using Verilog/SystemVerilog.
- Collaborate with architecture, verification, and implementation teams to improve model outputs.
- Develop reusable verification components and testbench infrastructure.
- Leverage LLM-based tools to accelerate chip design and verification processes.
- Work independently and asynchronously to meet project deadlines.
Qualifications
Must-Have
- 3–10 years of experience in digital RTL design or design verification.
- Strong proficiency in Verilog/SystemVerilog and UVM.
- Solid understanding of digital design fundamentals: FSMs, datapaths, pipelines, FIFOs, arbiters, clock/reset domains, bus protocols.
- Experience with ASIC design flows and common EDA tools.
- Ability to write clear design documentation and communicate technical tradeoffs.
Preferred
- Knowledge of AMBA protocols (AXI, AHB, APB).
- Background in CPU, GPU/ML accelerator, networking, memory subsystem, PCIe/high-speed IO, SoC interconnect, low-power design.
- Exposure to formal verification or SV/UVM-based design verification.
Start Date
- Week of 04/23; applications reviewed on a rolling basis.
Compensation & Legal
- Hourly contractor, Paid weekly.
Application Process (Takes 20–30 mins to complete)
- Upload resume
- AI interview based on your resume
- Submit form
Resources & Support
- For details about the interview process and platform information, please check: https://talent.docs.mercor.com/welcome
- For any help or support, reach out to: support@mercor.com
PS: Our team reviews applications daily. Please complete your AI interview and application steps to be considered for this opportunity.