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Ai Chip Design Rtl Jobs in New York (NOW HIRING)

Normal Computing

Hardware Engineer, RTL

New York, NY · On-site

$200K - $285K/yr

Experience at an AI chip company where design and verification were tightly coupled * Open-source RTL contributions to projects like Chipyard, OpenTitan, or CVA6 * Familiarity with RISC-V or other ...

Jane Street

ASIC Physical Design Engineer

New York, NY · On-site

$148K - $153K/yr

... chip designers. You should be comfortable owning a PD flow end-to-end, but also able to read and write RTL and reason about design decisions that cross the front-end/back-end boundary. If you've ...

Jane Street

ASIC Physical Design Engineer

New York, NY · On-site

$148K - $153K/yr

... chip designers. You should be comfortable owning a PD flow end-to-end, but also able to read and write RTL and reason about design decisions that cross the front-end/back-end boundary. If you've ...

Nvidia

Senior VLSI CAD Software Engineer

New York, NY · On-site

$134K - $176K/yr

... AI to define the next era of computing. An era in which our GPU acts as the brains of computers ... Design, development, review, test, and support of high-capacity and high-performance chip design ...

Normal Computing

AI Engineer

New York, NY · On-site

$200K - $300K/yr

The Role As an AI Engineer at Normal, you will build production systems that understand large technical documents, like chip design specifications, and turn them into code. You'll ship real ...

Virtusa Corporation

Vice President

New York, NY · On-site

... chip design services at scale. Focused exclusively on microchip design, embedded solutions and AI ... RTL design through physical implementation, verification, and tape-out management. Our clients span ...

Virtusa

Vice President

New York, NY

... chip design services at scale. Focused exclusively on microchip design, embedded solutions and AI ... RTL design through physical implementation, verification, and tape-out management. Our clients span ...

Virtusa

Vice President

New York, NY

... chip design services at scale. Focused exclusively on microchip design, embedded solutions and AI ... RTL design through physical implementation, verification, and tape-out management. Our clients span ...

Siemens

Research Scientist, Physics x AI

New York, NY · On-site

AI-native electronic design automation (EDA) and chip design * Any other discipline where physical or biological priors in AI can bring breakthrough scale and generalization A research scientist in ...

Cloud Peritus

Hardware Engineer

New York, NY · On-site

$135K - $178K/yr

Strong skills in RTL design (SystemVerilog) and verification. Strong working knowledge of Xilinx design flows (synthesis, place & route, timing analysis). Knowledge of TCP/IP stack and on-chip ...

Cloud Peritus

Hardware Engineer

New York, NY · On-site

$135K - $178K/yr

... RTL design (SystemVerilog) and verification. • Strong working knowledge of Xilinx design flows (synthesis, place & route, timing analysis). • Knowledge of TCP/IP stack and on-chip networking ...

Normal Computing

Hardware Engineer, FPGA

New York, NY · On-site

$200K - $280K/yr

We co-design the full stack: AI-native EDA systems in production with the world's largest ... RTL Implementation : Adapt and implement complex ASIC RTL onto FPGA targets, including multi-clock ...

Airspan

FPGA DESIGN ENGINEER

Warren, NJ · On-site

$127K - $176K/yr

Develop RTL designs in Verilog/System Verilog , ensuring efficient and high-performance ... Preferred Skills: * Experience with FPGA-based acceleration for AI/ML applications

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Ai Chip Design Rtl information

What is a $900000 AI job?

A $900,000 AI job typically refers to a high-level position in artificial intelligence, such as senior AI researcher, machine learning engineer, or AI architect, often requiring advanced skills in deep learning, neural networks, and hardware design like RTL for AI chips. Such roles usually involve leadership, extensive experience, and may include stock options or bonuses, with compensation reflecting expertise and impact on AI hardware development.

What is the difference between Ai Chip Design Rtl vs Ai Chip Verification Engineer?

AspectAi Chip Design RtlAi Chip Verification Engineer
Primary FocusDeveloping and implementing Register Transfer Level (RTL) code for AI chipsVerifying and validating RTL designs to ensure functionality
Skills RequiredHDL languages (Verilog/VHDL), digital design, FPGA/ASIC knowledgeSimulation, testbench creation, debugging, scripting skills
Work EnvironmentDesign teams, hardware development labs, EDA toolsVerification teams, simulation environments, test setups
CertificationsHardware design certifications, FPGA/ASIC trainingVerification methodologies, UVM, SystemVerilog certifications

While Ai Chip Design Rtl focuses on creating the hardware description code for AI chips, Ai Chip Verification Engineer ensures that the RTL design functions correctly through rigorous testing. Both roles require knowledge of HDL languages and work closely within hardware development teams, but their core responsibilities differ—design versus verification.

Will AI replace RTL designers?

AI chip design RTL (Register Transfer Level) development involves creating hardware descriptions that require expert knowledge of digital logic and hardware architecture. While AI tools can assist in automating certain tasks like code generation and verification, they are unlikely to fully replace RTL designers, as human expertise is essential for complex decision-making, optimization, and ensuring design correctness. RTL designers will continue to play a critical role in the chip design process, often working alongside AI-assisted tools to improve efficiency and innovation.

What are some common challenges faced by AI Chip Design RTL engineers during the verification process?

AI Chip Design RTL engineers often encounter challenges in ensuring their designs meet complex functional and performance requirements, especially given the rapid pace of AI hardware advancements. Verification can be particularly demanding due to the need to simulate and test intricate AI workloads, manage large datasets, and debug subtle timing or logic errors. Collaboration with verification teams, system architects, and software engineers is essential to address these issues efficiently and to ensure seamless integration of the RTL code into the broader chip design. Staying up-to-date with the latest verification tools and methodologies is also crucial for success in this role.

Which 3 jobs will survive AI?

AI Chip Design RTL professionals are likely to continue in demand due to the specialized technical skills required for hardware description languages like Verilog and VHDL, which are less easily automated. Jobs involving complex problem-solving, system integration, and hardware-software interface design, such as hardware engineers, system architects, and verification engineers, are also expected to persist. These roles require domain expertise and critical thinking that complement AI automation capabilities.

What are AI Chip Design RTL engineers?

AI Chip Design RTL (Register Transfer Level) engineers are specialists who design the digital logic for chips used in artificial intelligence applications. They use hardware description languages like Verilog or VHDL to create and validate the architecture and functionality of these chips before they are manufactured. Their work ensures that AI processors are efficient, high-performing, and meet the requirements of modern AI workloads. RTL engineers collaborate closely with verification, software, and hardware teams to optimize chip performance and power consumption.

What is the salary of RTL design?

The salary for an RTL (Register Transfer Level) design engineer typically ranges from $80,000 to $150,000 annually, depending on experience, location, and company size. Entry-level positions may start lower, while experienced engineers with specialized skills in hardware description languages like VHDL or Verilog can earn higher salaries.

What are the key skills and qualifications needed to thrive as an AI Chip Design RTL Engineer, and why are they important?

To thrive as an AI Chip Design RTL Engineer, you need a solid background in digital design, computer architecture, and proficiency in Hardware Description Languages (HDLs) like Verilog or VHDL, often supported by a degree in electrical or computer engineering. Experience with simulation tools (e.g., ModelSim, Synopsys), ASIC/FPGA design flows, and relevant certifications are highly valued. Strong problem-solving abilities, attention to detail, and effective teamwork and communication skills help you excel in collaborative and complex design environments. These competencies are crucial for creating efficient, reliable AI hardware that meets performance and power requirements in a fast-evolving field.
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Ai Chip Design Rtl jobs near you
Infographic showing various Ai Chip Design Rtl job openings in New York as of July 2026, with employment types broken down into 75% Full Time, 22% Part Time, and 3% Contract. Highlights an 71% Physical, 3% Hybrid, and 26% Remote job distribution.

Hardware Engineer, RTL

Normal Computing

New York, NY • On-site

$200K - $285K/yr

Full-time

Posted 27 days ago

Job description

About Normal Computing
Normal Computing builds silicon that turns thermal noise from an obstacle into a computational resource. Conventional chips spend most of their energy forcing determinism onto physics; ours compute with it. Stochastic, in-memory, asynchronous: the result is 10-100× more AI inference per dollar, per watt.
We co-design the full stack: AI-native EDA systems in production with the world's largest semiconductor companies, and the advanced ASICs they make possible. Backed by $85M+ from the world's leading deep-tech investors and built by scientists, engineers, and operators from the labs that built modern computing.
Normal works as one team across New York, Silicon Valley, London, Copenhagen, and Seoul. We hire people who want the hardest version of their craft, across every discipline, at every seniority.
The Role
As an RTL Design Engineer at Normal, you will design and verify the digital logic at the heart of Normal's thermodynamic hardware. This work sits at the intersection of classical ASIC design, novel computing architectures, and a development environment where the hardware and the algorithms are built together, not in sequence.
You will own RTL from microarchitecture to tapeout: writing microarchitecture specifications, creating synthesizable SystemVerilog, working with design verification engineers fully test the design using conventional and formal methods, and working closely physical design to make sure the design meets area and timing constraints. Because Normal's chips are not standard accelerators, the RTL engineer here is closer to first-principles decisions than at a larger company. You will be shaping architecture, not just implementing it.
This is a role for an engineer who collaborates effectively across teams, including architecture, verification and physical design. The strongest candidates have taped out silicon, written RTL and helped close coverage, and are comfortable working in an environment where the specification is still being developed in parallel.
What You'll Own
  • RTL Design: Write and own synthesizable RTL in SystemVerilog across blocks ranging from datapath logic to control and memory interfaces.
  • Microarchitecture: Work with architecture to translate high-level specifications into implementable microarchitectures.
  • Verification: Work closely with the verification team to review verification plans, assist on debug, and become a partner in closing coverage.
  • Physical Design Collaboration: Collaborate with physical design on timing closure, floorplanning constraints, and DFT.
  • Design Reviews: Participate in design reviews and contribute to architecture decisions, not just implementation.
  • Tapeout & Bring-up: Support tapeout preparation, integration, and post-silicon bring-up as needed.

What Makes You a Great Fit
  • Hands-on experience writing production RTL in SystemVerilog and closing it through synthesis and place-and-route
  • Experience in closing coverage to a high level
  • At least one tapeout in your background, from any node and any company size
  • Experience working on datapaths, pipelines, or custom logic where the microarchitecture was not fully specified upfront
  • Strong debugging instincts across simulation, waveforms, and formal counterexamples
  • Ability to work directly with architects and physical designers without needing a large intermediary layer
  • Industry experience in ASIC or SoC design

Bonus Points
  • Experience at an AI chip company where design and verification were tightly coupled
  • Open-source RTL contributions to projects like Chipyard, OpenTitan, or CVA6
  • Familiarity with RISC-V or other open ISAs
  • Experience with AI-assisted RTL or EDA tooling in your design workflow
  • Exposure to physical design constraints, floorplanning, or timing-driven RTL development

Equal Employment Opportunity Statement
Normal Computing is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other legally protected status.
Accessibility Accommodations
Normal Computing is committed to providing reasonable accommodations to individuals with disabilities. If you need assistance or an accommodation due to a disability, please let us know at accommodations@normalcomputing.com.
Privacy Notice
By submitting your application, you agree that Normal Computing may collect, use, and store your personal information for employment-related purposes in accordance with our Privacy Policy.

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