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Formal Verification Engineer Jobs (NOW HIRING)

Apple

GPU Formal Design Verification Engineer

Austin, TX

$134K - $164K/yr

The Graphics Verification Engineer will be responsible for the pre-silicon RTL verification applying formal and property checking methods. This includes deep understanding of the micro-architectural ...

Nvidia

Senior Formal Verification Engineer

Austin, TX

$103K - $142K/yr

As a Formal Verification Engineer at NVIDIA, you will verify the build and implementation of the industry's leading GPUs. In this position, your responsibilities will be to verify the micro ...

Nvidia

Senior Formal Verification Engineer

Santa Clara, CA · On-site

$122K - $168K/yr

As a Formal Verification Engineer at NVIDIA, you will verify the build and implementation of the industry's leading GPUs. In this position, your responsibilities will be to verify the micro ...

Micron

SOC Formal Verification Engineer, HBM

Richardson, TX · On-site

$123K - $150K/yr

Collaborate with RTL designers, architects, and simulation-based verification engineers to resolve bugs and clarify design intent. * Support block-level and subsystem-level formal verification, with ...

Waymo

Senior Formal Verification Engineer

Mountain View, CA · On-site

$204K - $259K/yr

Serve as the team's formal Subject Matter Expert, training and guiding logic designers and verification engineers to effectively incorporate formal methods into their workflows * Strategic planning ...

Nvidia

Senior Formal Verification Engineer

Santa Clara, CA · On-site

$122K - $168K/yr

As a Formal Verification Engineer at NVIDIA, you will verify the build and implementation of the industry's leading GPUs. In this position, your responsibilities will be to verify the micro ...

Nvidia

OR · Hybrid

$104K - $143K/yr

As a Senior Formal Verification Engineer at NVIDIA, you will verify ASICs developed at the forefront using formal verification tools. You will define the verification scope and ensure correctness.

Etched

Formal Verification - DV

San Jose, CA · On-site

$2.0K/mo

Job Summary We are seeking a Formal Verification Engineer to join our ASIC Design Verification team. You will drive formal verification across the custom IP, interface IP, and SoC subsystems that ...

Apple

Formal Verification - AI/ML Engineer

Austin, TX · On-site

$134K/yr

Apple's Hardware Technologies Formal Verification team is seeking an AI/ML Engineer to work at the intersection of Artificial Intelligence and Formal Verification. In this role, you will explore ...

Nvidia

Join our outstanding team as a Senior Formal Verification Engineer and be at the forefront of developing modern technology that builds the future. This role offers an outstanding opportunity to work ...

Nvidia

OR · Hybrid

Join our outstanding team as a Senior Formal Verification Engineer and be at the forefront of developing modern technology that builds the future. This role offers an outstanding opportunity to work ...

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All JobsFormal Verification Engineer Jobs

Formal Verification Engineer information

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$80K

$142.6K

$203.5K

How much do formal verification engineer jobs pay per year?

As of Jun 24, 2026, the average yearly pay for formal verification engineer in the United States is $142,619.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $136,000.00 per year, depending on experience, location, and employer.

What do formal verification engineers do?

Formal verification engineers develop and apply mathematical methods to prove the correctness of hardware and software designs, ensuring they meet specified requirements. They use tools like model checkers and theorem provers, often working closely with design teams to identify and eliminate errors early in the development process.

What engineers make $500,000?

Senior engineers in specialized fields such as software engineering, data engineering, or hardware design can earn $500,000 or more annually, especially with extensive experience, advanced skills, and leadership roles. High compensation often includes bonuses, stock options, or profit sharing, particularly in technology companies or executive positions.

What are the key skills and qualifications needed to thrive in the Formal Verification Engineer position, and why are they important?

To thrive as a Formal Verification Engineer, you need a strong background in digital design, computer architecture, and logic, typically supported by a degree in electrical engineering, computer science, or a related field. Expertise in formal verification tools such as Cadence JasperGold, Synopsys VC Formal, or Mentor Questa, along with proficiency in hardware description languages (HDLs) like Verilog or VHDL, is essential. Strong analytical thinking, attention to detail, and effective communication skills help you collaborate with design and verification teams and present complex findings. These competencies are critical for ensuring hardware systems are bug-free, reliable, and meet stringent industry standards.

How much does a verification engineer make in the US?

Verification engineers in the US typically earn between $80,000 and $130,000 annually, depending on experience, location, and industry. Senior roles or those with specialized skills in hardware description languages and verification tools can earn higher salaries. Entry-level positions generally start around $70,000 to $90,000.

Are verification engineers in demand?

Verification engineers are in high demand due to the increasing complexity of hardware and integrated circuits, especially in industries like semiconductor, aerospace, and automotive. Employers seek professionals skilled in hardware description languages, simulation tools, and formal verification methods to ensure product reliability and performance.

What are the common daily responsibilities of a Formal Verification Engineer?

As a Formal Verification Engineer, your typical day involves creating and analyzing formal properties, developing assertions, and using formal verification tools to mathematically prove correctness of hardware designs. You'll collaborate closely with design and simulation teams to review specifications, identify verification requirements, and debug issues found during the verification process. Regular documentation of findings, participation in code and design reviews, and ongoing learning about new verification methodologies are also important parts of the role. This dynamic environment requires both technical depth and proactive teamwork to ensure high-quality design outcomes.

What is a Formal Verification Engineer job?

A Formal Verification Engineer is responsible for ensuring the correctness of hardware or software designs using mathematical and logical techniques. They apply formal methods to verify that a system behaves as intended, identifying potential design flaws early in the development process. This involves writing formal properties, using model checking tools, and collaborating with design and validation teams. Their work helps improve reliability, reduce bugs, and enhance the efficiency of verification compared to traditional simulation-based methods.

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Formal Verification Engineer jobs near you
Infographic showing various Formal Verification Engineer job openings in the United States as of June 2026, with employment types broken down into 2% As Needed, 94% Full Time, 2% Part Time, and 2% Contract. Highlights an 93% Physical, 1% Hybrid, and 6% Remote job distribution, with an average salary of $142,619 per year, or $68.6 per hour.
Senior Formal Hardware Verification Engineer

Senior Formal Hardware Verification Engineer

Correct Designs

Austin, TX • On-site, Remote

$109K - $146K/yr

Other

Medical, Retirement

Posted 17 days ago

Job description

Current Openings >> Senior Formal Hardware Verification Engineer
Senior Formal Hardware Verification Engineer
Summary
Title: Senior Formal Hardware Verification Engineer ID: 1062 Location: Austin, TX
More about this job >
Description

Senior Formal Verification Engineer

Looking for new challenges?  Would you like the variety of a contract position along with long term stability and benefits? Correct Designs can give it all to you.

Correct Designs is currently seeking talented Formal Verification Engineers with experience working with a formal verification tool: Cadence Jasper, Mentor Quest FV or Synopsys VC Formal (Hector). Correct Designs has opportunities in a wide range of products including projects in AI and Machine Learning, processor fabric subsystems, SOC/ASIC products for vision processing, aerospace FPGAs, medical electronics, RISC-V based SoC, ARM based peripherals, and mixed signal DSPs. Successful candidates for this role will support verification of advanced CPU/GPU based SOCs.  

Correct Designs is NOT the typical contracting, staff augmentation firm.  Our engineers have respected long term roles with generous hourly rates in excellent team environments.  A typical contract may last 3 years, although we have shorter and even longer term work available. We are well respected in the Design Verification community with clients always seeking new CDI engineers. If you need a few months off between contracts you can take that break and know there will be plenty of work available when you return.  If you like the stability of always working, simply move to the next contract with little time off. Correct Designs does provide health care and retirement plan benefits.

We are based in Austin, Texas with clients throughout the US.  This position is located in Austin, TX.  We would prefer someone located in Austin, TX, but we are open to remote work.
Whether you are an experienced veteran looking for new challenges, or a talented engineer seeking to broaden your experience, we can offer exciting options for your career.  
Correct Designs uses E-Verify to confirm work status eligibility.
 

RESPONSIBILITIES:

  • Verify complex design blocks formal verification methods
  • Develop and execute pre-silicon verification test plans
  • Develop directed and random verification tests to validate block and IP functionality
  • Develop verification components and tools
  • Develop verification functional coverage using industry standard coverage analysis tools/methods
  • Debug regression fails 
  • Replicate functional issues found in external environments or post-silicon; review/enhance tests to verify bug fixes

 REQUIRED SKILLS AND EXPERIENCE:

  • 8 or more years of proven verification experience in a hardware development setting
  • Strong background in Formal verification methodologies
  • Strong debug skills and experience with debug tools such as DVE/Verdi
  • Proficiency in Object Oriented programming, computer architecture and data structures
  • Strong analytical/problem solving skills and pronounced attention to details
  • Strong interpersonal and communication skills
  • Must be comfortable working across geographies

DESIRED SKILLS:

  • Experience architecting/developing verification environments and infrastructure, including scripting using Perl, Ruby, Make, or similar
  • Experience in other related domains such as formal verification, RTL design, or software development

 EDUCATION:

Bachelor or Master's in Electrical Engineering, Computer Engineering, or Computer Science

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