VHDL, Verilog, System verilog and OVM, Perl, C, Specman Tools: ModelSim (Questa), Specman
VHDL, Verilog, System verilog and OVM, Perl, C, Specman Tools: ModelSim (Questa), Specman
Senior FPGA Engineer - Verilog, Digital Logic Design
Austin, TX · On-site
$140K - $170K/yr
What you get to do: -Design and develop embedded systems built on FPGA technology -Create digital logic design using Verilog / SystemVerilog -Implement high-speed DSP algorithms in digital logic ...
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Senior FPGA Engineer - Verilog, Digital Logic Design
Austin, TX · On-site
$140K - $170K/yr
What you get to do: -Design and develop embedded systems built on FPGA technology -Create digital logic design using Verilog / SystemVerilog -Implement high-speed DSP algorithms in digital logic ...
Design Verification Engineer - Verification Lead - UVM / System Verilog / RTL Verification
Austin, TX · On-site
$70 - $80/hr
System Verilog * RTL Verification Role Overview: We are seeking a seasoned Verification Lead with expertise or strong interest in IO/PHY verification. The ideal candidate will have a proven track ...
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Design Verification Engineer - Verification Lead - UVM / System Verilog / RTL Verification
Austin, TX · On-site
$70 - $80/hr
System Verilog * RTL Verification Role Overview: We are seeking a seasoned Verification Lead with expertise or strong interest in IO/PHY verification. The ideal candidate will have a proven track ...
Required qualifications include a Bachelor's degree in a related field and proficiency in System Verilog. This position offers competitive compensation and benefits, with a focus on substantial ...
Required qualifications include a Bachelor's degree in a related field and proficiency in System Verilog. This position offers competitive compensation and benefits, with a focus on substantial ...
Analog/Mixed Signal Verilog Modeling Design Engineer
$120K - $192K/yr
Understand Verilog-AMS modeling language * Good knowledge of SystemVerilog UDT/UDR nettype (using Cadence wreal or EEnet package) * Familiar with analog circuits such as LDOs, TIAs, analog muxing ...
Analog/Mixed Signal Verilog Modeling Design Engineer
$120K - $192K/yr
Understand Verilog-AMS modeling language * Good knowledge of SystemVerilog UDT/UDR nettype (using Cadence wreal or EEnet package) * Familiar with analog circuits such as LDOs, TIAs, analog muxing ...
Analog/Mixed Signal Verilog Modeling Design Engineer
Irvine, CA · On-site
$120K - $192K/yr
Understand Verilog-AMS modeling language * Good knowledge of SystemVerilog UDT/UDR nettype (using Cadence wreal or EEnet package) * Familiar with analog circuits such as LDOs, TIAs, analog muxing ...
Analog/Mixed Signal Verilog Modeling Design Engineer
Irvine, CA · On-site
$120K - $192K/yr
Understand Verilog-AMS modeling language * Good knowledge of SystemVerilog UDT/UDR nettype (using Cadence wreal or EEnet package) * Familiar with analog circuits such as LDOs, TIAs, analog muxing ...
Logic design, implementation, and verification using Verilog, System Verilog, and any required programing and scripting languages. * Synthesize and optimize RTL for timing, area and power.
Logic design, implementation, and verification using Verilog, System Verilog, and any required programing and scripting languages. * Synthesize and optimize RTL for timing, area and power.
The candidate should be familiar with C, C++ and Verilog and/or VHDL. Must be able to work with supervision from more experienced engineers and engage in technical dialogue. The candidate should be ...
The candidate should be familiar with C, C++ and Verilog and/or VHDL. Must be able to work with supervision from more experienced engineers and engage in technical dialogue. The candidate should be ...
Thermal Engineer
San Jose, CA · On-site
$60/hr
Defining and implementing test plans, developing System Verilog /UVM based unit level test benches, including stimulus, checkers, monitors and assertions, analyzing and debugging regression fails ...
Thermal Engineer
San Jose, CA · On-site
$60/hr
Defining and implementing test plans, developing System Verilog /UVM based unit level test benches, including stimulus, checkers, monitors and assertions, analyzing and debugging regression fails ...
Emulation Engineer
Austin, TX · On-site
$65/hr
Expertise in Verilog/System Verilog design and simulation. * Proficiency with FPGA synthesis and partitioning tools (e.g., Synplify, Vivado). * Experience with Synopsys HAPS prototyping platforms.
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Emulation Engineer
Austin, TX · On-site
$65/hr
Expertise in Verilog/System Verilog design and simulation. * Proficiency with FPGA synthesis and partitioning tools (e.g., Synplify, Vivado). * Experience with Synopsys HAPS prototyping platforms.
Principal Verification Engineer
Dallas, TX · On-site
$127.80K/yr
The Principal Verification Engineer will be responsible for architecting and creating verification environments using System-Verilog and Universal Verification Methodology (UVM) IPs and SoCs with ...
Principal Verification Engineer
Dallas, TX · On-site
$127.80K/yr
The Principal Verification Engineer will be responsible for architecting and creating verification environments using System-Verilog and Universal Verification Methodology (UVM) IPs and SoCs with ...
CPU Processor Power Management Verification Engineer
Santa Clara, CA · On-site
$159.70K/yr
Understanding of verification testplans, Verilog/System-Verilog testbenches, transactors and checkersKnowledge of system Verilog assertions or other advance verification techniques such as formal ...
CPU Processor Power Management Verification Engineer
Santa Clara, CA · On-site
$159.70K/yr
Understanding of verification testplans, Verilog/System-Verilog testbenches, transactors and checkersKnowledge of system Verilog assertions or other advance verification techniques such as formal ...
ASIC Design Engineer
San Diego, CA · On-site
Creating a constrained-random verification environment using System Verilog and UVM * Identifying and writing all types of coverage measures for stimulus and corner-cases * Debugging tests with ...
ASIC Design Engineer
San Diego, CA · On-site
Creating a constrained-random verification environment using System Verilog and UVM * Identifying and writing all types of coverage measures for stimulus and corner-cases * Debugging tests with ...
System IP / RTL Design Engineer
$99.10K - $135.80K/yr
... using Verilog and System Verilog • Experienced in setting up and maintaining front-end tools for Synthesis, LEC, Lint and Low Power Analysis • Excellent debug and problem-solving skills.
System IP / RTL Design Engineer
$99.10K - $135.80K/yr
... using Verilog and System Verilog • Experienced in setting up and maintaining front-end tools for Synthesis, LEC, Lint and Low Power Analysis • Excellent debug and problem-solving skills.
$125.80K - $153.60K/yr
Effective behavioural modelling and testing of circuits in Verilog and System Verilog, as well as logical equivalence verification between Schematic and Verilog models. UPF (Unified Power Format ...
$125.80K - $153.60K/yr
Effective behavioural modelling and testing of circuits in Verilog and System Verilog, as well as logical equivalence verification between Schematic and Verilog models. UPF (Unified Power Format ...
CPU Processor Power Management Verification Engineer
Santa Clara, CA · On-site
$159.70K/yr
Understanding of verification testplans, Verilog/System-Verilog testbenches, transactors and checkersKnowledge of system Verilog assertions or other advance verification techniques such as formal ...
CPU Processor Power Management Verification Engineer
Santa Clara, CA · On-site
$159.70K/yr
Understanding of verification testplans, Verilog/System-Verilog testbenches, transactors and checkersKnowledge of system Verilog assertions or other advance verification techniques such as formal ...
$135K - $170K/yr
Logic design, implementation, and verification using Verilog, System Verilog, and any required programing and scripting languages. * Synthesize andoptimize RTL for timing, area, and power. * Explore ...
$135K - $170K/yr
Logic design, implementation, and verification using Verilog, System Verilog, and any required programing and scripting languages. * Synthesize andoptimize RTL for timing, area, and power. * Explore ...
RTL Design and Verification
$139.20K - $169.90K/yr
Effective behavioural modelling and testing of circuits in Verilog and System Verilog, as well as logical equivalence verification between Schematic and Verilog models. UPF (Unified Power Format ...
RTL Design and Verification
$139.20K - $169.90K/yr
Effective behavioural modelling and testing of circuits in Verilog and System Verilog, as well as logical equivalence verification between Schematic and Verilog models. UPF (Unified Power Format ...
Design Verification Engineer
Austin, TX · On-site
$134.80K - $164.50K/yr
years of experience in pre-silicon design verification • Proficiency in C-shell scripting, Verilog-HDL & System Verilog. • Strong knowledge in SV Assertions, UVM/OVM and functional code coverage ...
Design Verification Engineer
Austin, TX · On-site
$134.80K - $164.50K/yr
years of experience in pre-silicon design verification • Proficiency in C-shell scripting, Verilog-HDL & System Verilog. • Strong knowledge in SV Assertions, UVM/OVM and functional code coverage ...
Verilog/System Verilog * GIT * Perl * Python * Tcl/Tk * C/C++ * Jenkins, Jira
Verilog/System Verilog * GIT * Perl * Python * Tcl/Tk * C/C++ * Jenkins, Jira
Verilog information
See salary details
$88K - $98.8K
9% of jobs
$98.8K - $109.6K
2% of jobs
$109.6K - $120.5K
2% of jobs
$120.5K - $131.3K
4% of jobs
$135.1K is the 25th percentile. Wages below this are outliers.
$131.3K - $142.1K
22% of jobs
$142.1K - $152.9K
4% of jobs
The median wage is $163.7K / yr.
$152.9K - $163.7K
6% of jobs
$173.1K is the 75th percentile. Wages above this are outliers.
$163.7K - $174.5K
29% of jobs
$174.5K - $185.4K
9% of jobs
$185.4K - $196.2K
6% of jobs
$196.2K - $207K
6% of jobs
$88K
$156.1K
$207K
How much do verilog jobs pay per year?
As of May 28, 2026, the average yearly pay for verilog in the United States is $156,077.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $175,500.00 per year, depending on experience, location, and employer.
What is a Verilog job?
A Verilog job typically involves designing, simulating, and verifying digital circuits using Verilog, a hardware description language (HDL). Engineers in this role work on FPGA and ASIC development for applications such as processors, communication systems, and embedded hardware. Responsibilities often include writing Verilog code, performing design synthesis, and debugging hardware using simulation tools. Verilog engineers are commonly employed in semiconductor, aerospace, and consumer electronics industries.
What are the key skills and qualifications needed to thrive in the Verilog position, and why are they important?
To excel in a Verilog role, you need a deep understanding of digital logic design, hardware description languages (especially Verilog), and often a degree in electrical or computer engineering. Experience with simulation tools like ModelSim, EDA tools such as Synopsys or Cadence, and potentially industry certifications like FPGA or ASIC design are highly valued. Strong analytical thinking, problem-solving skills, and effective teamwork are important soft skills in this field. These competencies are essential for creating reliable, efficient hardware designs and collaborating within multidisciplinary engineering teams.
What does a typical day-to-day workflow look like for someone working with Verilog?
A typical day in a Verilog role involves writing and modifying Verilog code to describe digital circuits, running simulations to verify design functionality, and debugging hardware issues in collaboration with other engineers. You might also interact with hardware engineers, verification teams, and project managers to ensure project milestones are met. Regular review meetings and design documentation are integral parts of the workflow, and you’ll often switch between independent tasks and team-based problem-solving. The work environment is usually dynamic and deadline-driven, offering opportunities to learn about cutting-edge hardware technologies.
More about Verilog jobs
What cities are hiring for Verilog jobs? Cities with the most Verilog job openings:
What are the most commonly searched types of Verilog jobs? The most popular types of Verilog jobs are:
What states have the most Verilog jobs? States with the most job openings for Verilog jobs include:
What job categories do people searching Verilog jobs look for? The top searched job categories for Verilog jobs are:
Contractor
Posted 20 days ago
Job description
Company Description
System Canada resources have a broad range of skills in different technologies. The large skill-set has been made possible by a conscious focus on strengthening our skills base. Every person selected for our team brings something new, something that adds to our offerings. We learn continuously, both on the job and through formal training programs.
Job Description
Recruitment agency can contact us.
This is only Corp to Corp
Duration: 1+ year
Location: Allentown PA
Key Skills Required :
Mandatory:
6+ years' experience in functional verification
At least 4+ experience using Specman
Experience in developing test plans based on specifications and requirements
Strong knowledge of functional verification tools and methodology
Experience developing verification components, large verification environments and tests for complex blocks
Coverage driven verification experience
Previous working experience on wireless SoC
Desirable:
Understanding of e Reuse Methodology (eRM)
Familiar with processor based SoC verification environments
Strong programming skills including object oriented approaches
Familiarity with revision control environments such as ClearCase
Strong written and verbal communication skills
Tools and Language:
Languages: VHDL, Verilog, System verilog and OVM, Perl, C, Specman
Tools: ModelSim (Questa), Specman
About System Canada
Sourced by ZipRecruiter
System Canada delivers high end solutions in corporate world. Our resources have a broad range of skills in different technologies.The large skill-set has been made possible by a conscious focus on strengthening our skills base. Every person selected for our team brings something new, something that adds to our offerings. We learn continuously, both on the job and through formal training programs.
Industry
It services
Company size
11 - 50 Employees
Headquarters location
Toronto, ON, CA