Verilog Jobs (NOW HIRING)

VHDL, Verilog, System verilog and OVM, Perl, C, Specman Tools: ModelSim (Questa), Specman

What you get to do: -Design and develop embedded systems built on FPGA technology -Create digital logic design using Verilog / SystemVerilog -Implement high-speed DSP algorithms in digital logic ...

Knowledge of Verilog, system Verilog and UVM is a must * Strong understanding of state of the art verification techniques, including assertion and constraint-random metric-driven verification

Staff Machine Learning Engineer, LLM Fine‑Tuning (Verilog/RTL Applications) We are looking for a Staff ML Engineer to lead fine-tuning and deployment of LLM‑based solutions for code/RTL workflows ...

Knowledge of Verilog, system Verilog and UVM is a must * Strong understanding of state of the art verification techniques, including assertion and constraint-random metric-driven verification

System Verilog * RTL Verification Role Overview: We are seeking a seasoned Verification Lead with expertise or strong interest in IO/PHY verification. The ideal candidate will have a proven track ...

A technology services company is seeking a Machine Learning Engineer specializing in LLM fine-tuning for Verilog/RTL applications. This mid-senior level role requires significant experience in ML/AI ...

Senior Digital Verification Engineer - UVM / System Verilog We are partnered with a global leader in high-speed optical networking and telecommunications connectivity solutions. The team is looking ...

Understand Verilog-AMS modeling language * Good knowledge of SystemVerilog UDT/UDR nettype (using Cadence wreal or EEnet package) * Familiar with analog circuits such as LDOs, TIAs, analog muxing ...

Understand Verilog-AMS modeling language * Good knowledge of SystemVerilog UDT/UDR nettype (using Cadence wreal or EEnet package) * Familiar with analog circuits such as LDOs, TIAs, analog muxing ...

Understand Verilog-AMS modeling language * Good knowledge of SystemVerilog UDT/UDR nettype (using Cadence wreal or EEnet package) * Familiar with analog circuits such as LDOs, TIAs, analog muxing ...

Logic design, implementation, and verification using Verilog, System Verilog, and any required programing and scripting languages. * Synthesize and optimize RTL for timing, area and power.

Expertise in Verilog/System Verilog design and simulation. * Proficiency with FPGA synthesis and partitioning tools (e.g., Synplify, Vivado). * Experience with Synopsys HAPS prototyping platforms.

The candidate should be familiar with C, C++ and Verilog and/or VHDL. Must be able to work with supervision from more experienced engineers and engage in technical dialogue. The candidate should be ...

Defining and implementing test plans, developing System Verilog /UVM based unit level test benches, including stimulus, checkers, monitors and assertions, analyzing and debugging regression fails ...

Creating a constrained-random verification environment using System Verilog and UVM * Identifying and writing all types of coverage measures for stimulus and corner-cases * Debugging tests with ...

The Principal Verification Engineer will be responsible for architecting and creating verification environments using System-Verilog and Universal Verification Methodology (UVM) IPs and SoCs with ...

Proficiency in SystemVerilog, Verilog, C, and C++ * Scripting experience with Python or similar automation languages * Developing UVM based verification frameworks and testbenches, processes and ...

Understanding of verification testplans, Verilog/System-Verilog testbenches, transactors and checkersKnowledge of system Verilog assertions or other advance verification techniques such as formal ...

Key skills are software (System Verilog, C/C++, object-oriented programming, scripting (e.g. Perl), x86 assembly), Verilog simulation and modeling, knowledge of computer and peripheral architectures.