San Jose, CA · On-site
$100 - $125/hr
Knowledge of Verilog, System Verilog and UVM is a must * Strong understanding of state of the art verification techniques, including assertion and constraint-random metric-driven verification
San Jose, CA · On-site
$100 - $125/hr
Knowledge of Verilog, System Verilog and UVM is a must * Strong understanding of state of the art verification techniques, including assertion and constraint-random metric-driven verification
San Jose, CA · On-site
$145K/yr
Knowledge of Verilog, system Verilog and UVM is a must * Strong understanding of state of the art verification techniques, including assertion and constraint-random metric-driven verification
San Jose, CA · On-site
$145K/yr
Knowledge of Verilog, system Verilog and UVM is a must * Strong understanding of state of the art verification techniques, including assertion and constraint-random metric-driven verification
San Jose, CA · Hybrid
$159K/yr
Knowledge of Verilog, system Verilog and UVM is a must * Strong understanding of state of the art verification techniques, including assertion and constraint-random metric-driven verification
San Jose, CA · Hybrid
$159K/yr
Knowledge of Verilog, system Verilog and UVM is a must * Strong understanding of state of the art verification techniques, including assertion and constraint-random metric-driven verification
San Jose, CA · On-site
Staff Machine Learning Engineer, LLM Fine‑Tuning (Verilog/RTL Applications) We are looking for a Staff ML Engineer to lead fine-tuning and deployment of LLM‑based solutions for code/RTL workflows ...
San Jose, CA · On-site
Staff Machine Learning Engineer, LLM Fine‑Tuning (Verilog/RTL Applications) We are looking for a Staff ML Engineer to lead fine-tuning and deployment of LLM‑based solutions for code/RTL workflows ...
A technology services company is seeking a Machine Learning Engineer specializing in LLM fine-tuning for Verilog/RTL applications. This mid-senior level role requires significant experience in ML/AI ...
A technology services company is seeking a Machine Learning Engineer specializing in LLM fine-tuning for Verilog/RTL applications. This mid-senior level role requires significant experience in ML/AI ...
Irvine, CA · On-site
$200 - $250/hr
Understand Verilog-AMS modeling language. Good knowledge of SystemVerilog UDT/UDR nettype (using Cadence wreal or EEnet package). Familiar with analog circuits such as LDOs, TIAs, analog muxing ...
Irvine, CA · On-site
$200 - $250/hr
Understand Verilog-AMS modeling language. Good knowledge of SystemVerilog UDT/UDR nettype (using Cadence wreal or EEnet package). Familiar with analog circuits such as LDOs, TIAs, analog muxing ...
Irvine, CA · On-site
$216K/yr
Understand Verilog-AMS modeling language * Good knowledge of SystemVerilog UDT/UDR nettype (using Cadence wreal or EEnet package) * Familiar with analog circuits such as LDOs, TIAs, analog muxing ...
Irvine, CA · On-site
$216K/yr
Understand Verilog-AMS modeling language * Good knowledge of SystemVerilog UDT/UDR nettype (using Cadence wreal or EEnet package) * Familiar with analog circuits such as LDOs, TIAs, analog muxing ...
San Jose, CA · On-site
$236K/yr
Understand Verilog-AMS modeling language * Good knowledge of SystemVerilog UDT/UDR nettype (using Cadence wreal or EEnet package) * Familiar with analog circuits such as LDOs, TIAs, analog muxing ...
San Jose, CA · On-site
$236K/yr
Understand Verilog-AMS modeling language * Good knowledge of SystemVerilog UDT/UDR nettype (using Cadence wreal or EEnet package) * Familiar with analog circuits such as LDOs, TIAs, analog muxing ...
Irvine, CA · On-site
$216K/yr
Understand Verilog-AMS modeling language * Good knowledge of SystemVerilog UDT/UDR nettype (using Cadence wreal or EEnet package) * Familiar with analog circuits such as LDOs, TIAs, analog muxing ...
Irvine, CA · On-site
$216K/yr
Understand Verilog-AMS modeling language * Good knowledge of SystemVerilog UDT/UDR nettype (using Cadence wreal or EEnet package) * Familiar with analog circuits such as LDOs, TIAs, analog muxing ...
San Jose, CA · On-site
$145K/yr
Proficiency in SystemVerilog, Verilog, C, and C++ * Scripting experience with Python or similar automation languages * Developing UVM based verification frameworks and testbenches, processes and ...
San Jose, CA · On-site
$145K/yr
Proficiency in SystemVerilog, Verilog, C, and C++ * Scripting experience with Python or similar automation languages * Developing UVM based verification frameworks and testbenches, processes and ...
San Jose, CA · Hybrid
$159K - $195K/yr
Proficiency in SystemVerilog, Verilog, C, and C++ * Scripting experience with Python or similar automation languages * Developing UVM based verification frameworks and testbenches, processes and ...
San Jose, CA · Hybrid
$159K - $195K/yr
Proficiency in SystemVerilog, Verilog, C, and C++ * Scripting experience with Python or similar automation languages * Developing UVM based verification frameworks and testbenches, processes and ...
Santa Clara, CA · On-site
$159K/yr
Understanding of verification testplans, Verilog/System-Verilog testbenches, transactors and checkers Knowledge of system Verilog assertions or other advance verification techniques such as formal ...
Santa Clara, CA · On-site
$159K/yr
Understanding of verification testplans, Verilog/System-Verilog testbenches, transactors and checkers Knowledge of system Verilog assertions or other advance verification techniques such as formal ...
San Diego, CA · On-site
Creating a constrained-random verification environment using System Verilog and UVM * Identifying and writing all types of coverage measures for stimulus and corner-cases * Debugging tests with ...
San Diego, CA · On-site
Creating a constrained-random verification environment using System Verilog and UVM * Identifying and writing all types of coverage measures for stimulus and corner-cases * Debugging tests with ...
Santa Clara, CA · On-site
$159K/yr
Understanding of verification testplans, Verilog/System-Verilog testbenches, transactors and checkers Knowledge of system Verilog assertions or other advance verification techniques such as formal ...
Santa Clara, CA · On-site
$159K/yr
Understanding of verification testplans, Verilog/System-Verilog testbenches, transactors and checkers Knowledge of system Verilog assertions or other advance verification techniques such as formal ...
Cupertino, CA · On-site
$167K/yr
... Verilog and System Verilog Good knowledge of Mixed signal concepts Good knowledge of Algorithm development Working experience with physical design teams Good Knowledge of front-end tools (Verilog ...
Cupertino, CA · On-site
$167K/yr
... Verilog and System Verilog Good knowledge of Mixed signal concepts Good knowledge of Algorithm development Working experience with physical design teams Good Knowledge of front-end tools (Verilog ...
Proficiency in System Verilog and advanced UVM methodologies is a must. * Good experience in System Verilog assertions. * Own the development of test plans, test environments and test suites used to ...
Proficiency in System Verilog and advanced UVM methodologies is a must. * Good experience in System Verilog assertions. * Own the development of test plans, test environments and test suites used to ...
San Jose, CA · On-site
$159K - $194K/yr
System Verilog,UVM,C+
San Jose, CA · On-site
$159K - $194K/yr
System Verilog,UVM,C+
San Jose, CA · On-site
$159K - $194K/yr
UVM,SOC,Verilog,ASIC
San Jose, CA · On-site
$159K - $194K/yr
UVM,SOC,Verilog,ASIC
VHDL, Verilog, System Verilog, and System Verilog Assertions (SVA), Experience with Formal Verification is a must Qualifications Experience in functional verification EDA tools: VCS, IUS, ModelSim ...
VHDL, Verilog, System Verilog, and System Verilog Assertions (SVA), Experience with Formal Verification is a must Qualifications Experience in functional verification EDA tools: VCS, IUS, ModelSim ...
Irvine, CA · On-site
$100 - $125/hr
Design, implement, and maintain Verification environments using System Verilog and UVM. * Apply constrained random verification techniques and drive coverage closure. * Collaborate with design ...
Irvine, CA · On-site
$100 - $125/hr
Design, implement, and maintain Verification environments using System Verilog and UVM. * Apply constrained random verification techniques and drive coverage closure. * Collaborate with design ...
$86.8K - $97.5K
9% of jobs
$97.5K - $108.2K
2% of jobs
$108.2K - $118.9K
2% of jobs
$118.9K - $129.6K
4% of jobs
$133.4K is the 25th percentile. Wages below this are outliers.
$129.6K - $140.2K
22% of jobs
$140.2K - $150.9K
4% of jobs
The median wage is $161.6K / yr.
$150.9K - $161.6K
6% of jobs
$170.9K is the 75th percentile. Wages above this are outliers.
$161.6K - $172.3K
29% of jobs
$172.3K - $182.9K
9% of jobs
$182.9K - $193.6K
6% of jobs
$193.6K - $204.3K
6% of jobs
$86.8K
$154K
$204.3K
A Verilog job typically involves designing, simulating, and verifying digital circuits using Verilog, a hardware description language (HDL). Engineers in this role work on FPGA and ASIC development for applications such as processors, communication systems, and embedded hardware. Responsibilities often include writing Verilog code, performing design synthesis, and debugging hardware using simulation tools. Verilog engineers are commonly employed in semiconductor, aerospace, and consumer electronics industries.
A typical day in a Verilog role involves writing and modifying Verilog code to describe digital circuits, running simulations to verify design functionality, and debugging hardware issues in collaboration with other engineers. You might also interact with hardware engineers, verification teams, and project managers to ensure project milestones are met. Regular review meetings and design documentation are integral parts of the workflow, and you’ll often switch between independent tasks and team-based problem-solving. The work environment is usually dynamic and deadline-driven, offering opportunities to learn about cutting-edge hardware technologies.
To excel in a Verilog role, you need a deep understanding of digital logic design, hardware description languages (especially Verilog), and often a degree in electrical or computer engineering. Experience with simulation tools like ModelSim, EDA tools such as Synopsys or Cadence, and potentially industry certifications like FPGA or ASIC design are highly valued. Strong analytical thinking, problem-solving skills, and effective teamwork are important soft skills in this field. These competencies are essential for creating reliable, efficient hardware designs and collaborating within multidisciplinary engineering teams.
The most popular types of Verilog jobs in California are:
For Verilog jobs in California, the most frequently searched job titles are:
The top searched job categories for Verilog jobs in California are:
Cities in California with the most Verilog job openings:
$100 - $125/hr
Other
Re-posted 17 hours ago
8.6
Based on 13 frontline employees who took The Breakroom Quiz
26th of 161 rated electronics manufacturers
WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.
Together, we advance your career.
THE ROLEAs a member of the Front-End Verification team, you will play a critical role in validating the functional correctness of next-generation AMD/Xilinx programmable devices. Working across a multi-site, global engineering organization, you will drive high-quality verification execution from feature definition through silicon readiness.
THE PERSONYou are passionate about digital design and advanced verification methodologies. You thrive in collaborative, cross-functional environments and communicate effectively across sites and time zones. With strong analytical and problem-solving skills, you take ownership of complex technical challenges and are motivated to continuously learn and improve.
KEY RESPONSIBILITIESSan Jose, CA
This role is not eligible for visa sponsorship.Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s "Responsible AI Policy" is available here.
This posting is for an existing vacancy.
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Computer and electronic product manufacturing and manufacturing
5,001 - 10,000 Employees
Sunnyvale, CA, US
