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Verilog Engineer Jobs in California (NOW HIRING)

OMNIVISION

SoC Design Engineer

Santa Clara, CA

$156K - $160K/yr

SoC Design Engineer Job Duties: Be responsible for digital design of ASIC cores within image sensor ... Design and design debug with System Verilog; Logic design and analysis. * Processing Subsystem ...

OMNIVISION

SoC Design Engineer

Santa Clara, CA · On-site

$156K - $160K/yr

SoC Design Engineer Job Duties: Be responsible for digital design of ASIC cores within image sensor ... Design and design debug with System Verilog; Logic design and analysis. * Processing Subsystem ...

OMNIVISION

SoC Design Engineer

Santa Clara, CA

SoC Design Engineer Job Duties: Be responsible for digital design of ASIC cores within image sensor ... Design and design debug with System Verilog; Logic design and analysis. * Processing Subsystem ...

OMNIVISION

Quality Engineer

Santa Clara, CA

$120K - $125K/yr

Verilog programming * Semiconductor physics * Reliability prediction Annual base salary for this role in California, US is expected to be between $120,182 - $125,000. Actual pay will be determined on ...

OMNIVISION

Quality Engineer

Santa Clara, CA

Verilog programming * Semiconductor physics * Reliability prediction Annual base salary for this role in California, US is expected to be between $120,182 - $125,000. Actual pay will be determined on ...

OMNIVISION

Quality Engineer

Santa Clara, CA · On-site

$120K - $125K/yr

Verilog programming * Semiconductor physics * Reliability prediction Annual base salary for this role in California, US is expected to be between $120,182 - $125,000. Actual pay will be determined on ...

OmniVision Technologies

Quality Engineer

Santa Clara, CA

$120K - $125K/yr

Verilog programming * Semiconductor physics * Reliability prediction Annual base salary for this role in California, US is expected to be between $120,182 - $125,000. Actual pay will be determined on ...

Cisco

ASIC Design Engineer Technical Lead

San Jose, CA

$186K - $267K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

Implement Verilog RTL to meet timing and performance requirements. * Help define, evolve, and support our design methodology. * Mentor junior engineers on performing project tasks and problem solving.

Cisco

ASIC Design Engineer Technical Lead

San Jose, CA · On-site

$186K - $267K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

Implement Verilog RTL to meet timing and performance requirements. * Help define, evolve, and support our design methodology. * Mentor junior engineers on performing project tasks and problem solving.

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All JobsVerilog Engineer JobsVerilog Engineer Jobs in California

Verilog Engineer information

See California salary details

$38.5K

$100.4K

$135.7K

How much do verilog engineer jobs pay per year?

As of Aug 14, 2026, the average yearly pay for verilog engineer in California is $100,420.00, according to ZipRecruiter salary data. Most workers in this role earn between $82,900.00 and $115,000.00 per year, depending on experience, location, and employer.

What is a Verilog engineer?

A Verilog Engineer is a hardware design professional who specializes in using the Verilog hardware description language (HDL) to design, simulate, and verify digital circuits. They work on developing FPGA and ASIC designs for applications in industries such as telecommunications, automotive, and consumer electronics. Their role often includes writing Verilog code, running simulations, debugging hardware issues, and optimizing performance. They collaborate with systems engineers and verification teams to ensure the correctness and efficiency of digital designs.

What are the key skills and qualifications needed to thrive in the Verilog engineer position, and why are they important?

To thrive as a Verilog Engineer, you need strong proficiency in digital design principles, solid experience with hardware description languages (HDLs) like Verilog, and usually a degree in electrical engineering or a related field. Familiarity with ASIC/FPGA design tools such as ModelSim, Synopsys, or Xilinx Vivado, and certifications in FPGA or hardware design can be advantageous. Attention to detail, strong problem-solving skills, and effective teamwork and communication abilities distinguish top performers in this role. These skills and qualities are crucial to efficiently designing, verifying, and delivering high-performance digital systems that meet project requirements and deadlines.

What are the typical daily responsibilities of a Verilog engineer?

A Verilog Engineer typically spends their day writing and verifying Verilog code to design and simulate digital logic circuits for ASICs or FPGAs. Their responsibilities include reviewing design specifications, collaborating with hardware and software teams, performing code reviews, and troubleshooting issues found during simulation or synthesis. They also document their work and may assist in optimizing designs for performance or resource utilization. Effective communication and teamwork are important, as Verilog Engineers often work closely with cross-functional engineering teams throughout the development cycle.

What are the most commonly searched types of Verilog Engineer jobs in California?

The most popular types of Verilog Engineer jobs in California are:

What are popular job titles related to Verilog Engineer jobs in California?

For Verilog Engineer jobs in California, the most frequently searched job titles are:

What job categories do people searching Verilog Engineer jobs in California look for?

The top searched job categories for Verilog Engineer jobs in California are:

Verilog Engineer jobs near you
Infographic showing various Verilog Engineer job openings in California as of August 2026, with employment types broken down into 67% Full Time, and 33% Contract. Highlights an 100% In-person job distribution, with an average salary of $100,420 per year, or $48.3 per hour.

FPGA Design Engineer (Verilog)

22nd Century Technologies, Inc. (TSCTI)

El Segundo, CA • On-site

$131K - $180K/yr

Other

Posted yesterday

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Job description

Job Title: FPGA Design Engineer (Verilog) Duration: 6 months assignment Shift Timing (Day/ Evening/ Night): First Shift (8 am to 4:30 pm) Job Description: The contractor will inherit FPGA top-level design and be responsible for creating and adding new functional blocks and interfaces, including integrating third-party and in-house IP cores. Responsibilities include updating constraint files, performing synthesis, simulation, and Place & Route processes to ensure timing closure and design integrity. The candidate will program FPGA devices, primarily from the Xilinx Versal, Ultrascale, and Ultrascale+ families. Additionally, the contractor will collaborate closely with the system engineering team to support hardware and software system integration as well as testing activities to deliver a fully functioning system. Therefore, on-site work is required. Required Skills: 5+ years of FPGA and/or ASIC design experience; Strong Xilinx/AMD Vivado experience; Experience with Versal family devices; Verilog/SystemVerilog HDL proficiency required; Advanced FPGA implementation skills (synthesis, timing closure, constraints); Active U.S. security clearance Preferred Skills: 2+ years of FPGA design experience; Strong Xilinx/AMD Vivado experience; Verilog/SystemVerilog proficiency; Advanced FPGA implementation skills (synthesis, timing closure, constraints); Required Experience: Education/experience typically acquired through advanced technical education from an accredited course of study in engineering, computer science, mathematics, physics or chemistry (e.g. Bachelor) and typically 14 or more years' related work experience (e.g. PhD+9 years' related work experience, Master+12 years' related work experience). In the USA, ABET accreditation is the preferred, although not required, accreditation standard.

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