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Rtl Jobs in California (NOW HIRING)

DensityAI

RTL Engineer

Mountain View, CA

$160K/yr

About the role Design the RTL that defines our AI accelerator. You'll architect and implement the digital blocks - compute datapath, memory subsystem, on-chip interconnect, and control logic - from ...

Mythic

RTL Design Engineer

Palo Alto, CA · On-site

$120K - $225K/yr

We're hiring experienced RTL Design Engineers from junior to senior levels to play a key role in designing and implementing the components that will bring our next-generation AI processors to life.

Velaura

RTL Lead

Santa Clara, CA · On-site

$200K - $500K/yr

Role Overview We are seeking an experienced RTL Lead to help drive the implementation of Velaura's next-generation Physical AI SoC. This role combines architectural influence with hands-on technical ...

Velaura

RTL Lead

Santa Clara, CA

$200K - $500K/yr

Role Overview We are seeking an experienced RTL Lead to help drive the implementation of Velaura's next-generation Physical AI SoC. This role combines architectural influence with hands-on technical ...

Mythic

RTL Design Engineer

Palo Alto, CA

$120K - $225K/yr

We're hiring experienced RTL Design Engineers from junior to senior levels to play a key role in designing and implementing the components that will bring our next-generation AI processors to life.

Mythic

RTL Design Engineer

Palo Alto, CA · On-site

$120K - $225K/yr

We're hiring experienced RTL Design Engineers from junior to senior levels to play a key role in designing and implementing the components that will bring our next-generation AI processors to life.

DensityAI

RTL Engineer

Mountain View, CA · On-site

$215K - $300K/yr

Own RTL design of digital blocks/subsystems for our accelerator - microarchitecture definition, SystemVerilog implementation, and integration * Translate architectural specs into efficient ...

Drive Capital

Hardware Engineer, RTL

Palo Alto, CA · On-site

$140 - $180/hr

The Role As an RTL Design Engineer at Normal, you will design and verify the digital logic at the heart of Normal\'s thermodynamic hardware. This work sits at the intersection of classical ASIC ...

Keylent Inc

RTL Design Engineer

Mountain View, CA · On-site

RTL Design Engineer Location - Mountain View, CA Duration: Full Time/ Contract Day 1 onsite Description: Responsibilities RTL, Arithmetic CPU, ALU, Design Processer, and resolving system level ...

Keylent Inc

RTL Design Engineer

Mountain View, CA · On-site

RTL Design Engineer Location - Mountain View, CA Duration: Full Time/ Contract Day 1 onsite Description: Responsibilities RTL, Arithmetic CPU, ALU, Design Processer, and resolving system level ...

Qualcomm

CPU RTL Methodology Engineer

Santa Clara, CA · On-site

$198K - $298K/yr

Support RTL development and debug workflows across CPU design teams. * Maintain and enhance RTL databases and repositories using GIT and other version control systems. * Triage RTL issues and ...

DensityAI

RTL Engineer

Mountain View, CA

$215K - $300K/yr

Own RTL design of digital blocks/subsystems for our accelerator -- microarchitecture definition, SystemVerilog implementation, and integration * Translate architectural specs into efficient ...

InterSources

ASIC RTL Design Engineer

Santa Clara, CA · On-site

ASIC RTL Design Engineer Responsible for microarchitecture and RTL design of high performance data processing chip. Micro-architecture definition, writing micro-architecture specifications. Write ...

InterSources

ASIC RTL Design Engineer

Santa Clara, CA · On-site

ASIC RTL Design Engineer Responsible for microarchitecture and RTL design of high performance data processing chip. Micro-architecture definition, writing micro-architecture specifications. Write ...

IBA Infotech Inc.

RTL Design Engineer

Santa Clara, CA · On-site

Role: (RTL) Design Engineer Location: Santa Clara, CA (Hybrid negotiable) Interview: Phone/Skype We're looking for a seasoned RTL engineer with 7+ years of experience in #RTLDesign #Verilog #VLSI ...

IBA Infotech Inc.

RTL Design Engineer

Santa Clara, CA · Hybrid

Role: (RTL) Design Engineer Location: Santa Clara, CA (Hybrid negotiable) Interview: Phone/Skype We're looking for a seasoned RTL engineer with 7+ years of experience in #RTLDesign #Verilog #VLSI ...

Mythic

Senior RTL Design Engineer

Palo Alto, CA · On-site

$120K - $225K/yr

We're hiring experienced RTL Design Engineers to play a key role in designing and implementing the components that will bring our next-generation AI processors to life. About Us: Mythic is building ...

Lumilens

IC/RTL Design Engineer

San Jose, CA · On-site

IC/RTL Design Engineer/ Front-End Engineer About the role. You design and implement the digital front-end RTL at the heart of the chip - including the high-speed datapath that moves data between UCIe ...

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All JobsRtl JobsRtl Jobs in California

Rtl information

See California salary details

$79.4K

$137.5K

$180.1K

How much do rtl jobs pay per year?

As of Sep 2, 2026, the average yearly pay for rtl in California is $137,543.00, according to ZipRecruiter salary data. Most workers in this role earn between $134,200.00 and $134,200.00 per year, depending on experience, location, and employer.

What is an RTL job?

RTL stands for 'Retail,' and RTL jobs generally refer to positions within the retail industry, such as sales associates, cashiers, store managers, and stock clerks. These roles involve assisting customers, managing inventory, operating cash registers, and ensuring the store environment is welcoming and organized. Retail jobs can be found in various settings, including clothing stores, supermarkets, electronics shops, and more. They often require strong communication skills, customer service abilities, and flexibility to work different shifts. Retail positions can offer opportunities for career growth and development within the industry.

What are the key skills and qualifications needed to thrive as a Retail Associate?

To thrive as a Retail Associate, you need strong customer service skills, basic math abilities, and a high school diploma or equivalent. Familiarity with point-of-sale (POS) systems, inventory management tools, and cash handling procedures is typically required. Outstanding communication, patience, and teamwork help you stand out in this fast-paced environment. These skills ensure efficient transactions, satisfied customers, and smooth store operations.

What are some common challenges faced by RTL (Register Transfer Level) design engineers, and how can they be addressed?

RTL Design Engineers often encounter challenges such as ensuring design correctness under tight schedules, managing complex verification requirements, and keeping up with evolving hardware description languages and EDA tools. Effective communication with verification teams and regular code reviews help catch logic errors early. Adopting best practices like modular design, thorough documentation, and continuous learning can make these challenges more manageable and ultimately contribute to successful project outcomes.

What is the difference between Rtl vs Speech-Language Pathologist?

AspectRtlSpeech-Language Pathologist
Required CredentialsTypically certification or training in Rtl techniquesMaster's degree in Speech-Language Pathology, state licensure, ASHA certification
Work EnvironmentEducational, clinical, or therapy settings focusing on communication skillsHospitals, schools, clinics, private practice
Industry UsageUsed in therapy and communication improvement programsHealthcare and educational sectors specializing in speech and language disorders

While Rtl (Response to Intervention) is a framework used to support students with learning and communication challenges, a Speech-Language Pathologist is a licensed professional who diagnoses and treats speech and language disorders. Rtl often guides intervention strategies, whereas Speech-Language Pathologists provide direct therapy and assessments. Both roles are integral in communication development but differ in credentials and scope of practice.

What are popular job titles related to Rtl jobs in California?

For Rtl jobs in California, the most frequently searched job titles are:

What job categories do people searching Rtl jobs in California look for?

The top searched job categories for Rtl jobs in California are:

What cities in California are hiring for Rtl jobs?

Cities in California with the most Rtl job openings:

Rtl jobs near you
Infographic showing various Rtl job openings in California as of August 2026, with employment types broken down into 93% Full Time, 5% Part Time, and 2% Contract. Highlights an 88% Physical, 7% Hybrid, and 5% Remote job distribution, with an average salary of $137,543 per year, or $66.1 per hour.

RTL Engineer

DensityAI

Mountain View, CA

$160K/yr

Full-time

Medical, Dental, Vision, Retirement, PTO

Re-posted 2 days ago

Job description

About the role

Design the RTL that defines our AI accelerator. You'll architect and implement the digital blocks - compute datapath, memory subsystem, on-chip interconnect, and control logic - from microarchitecture spec through synthesis-ready, timing-clean RTL, and own those blocks end-to-end with architecture, DV, physical design, and DFT all the way to silicon.

What You'll Do:
  • Own RTL design of digital blocks/subsystems for our accelerator - microarchitecture definition, SystemVerilog implementation, and integration
  • Translate architectural specs into efficient, synthesizable RTL that meets power/performance/area (PPA) targets
  • Drive microarchitecture trade-offs - pipelining, datapath vs. control, clock/power gating - for high-performance, low-power design
  • Partner with DV on verification, PD on synthesis/timing/floorplan closure, and DFT on testability
  • Own block-level quality: synthesis, timing/constraints (SDC, STA), lint, and CDC signoff
  • Contribute to architecture definition and design reviews; debug across simulation, emulation, and post-silicon bring-up
  • Use and develop AI-assisted tool flows to accelerate design and verification
What We're Looking For
  • Strong digital-design fundamentals and expert Verilog/SystemVerilog RTL
  • 5+ years designing complex digital blocks/SoCs taken to silicon
  • Solid microarchitecture skills - pipelining, datapath/control, FIFOs, arbitration, memory subsystems, on-chip interconnect/NoC
  • Synthesis & timing awareness - writing synthesizable RTL, SDC constraints, STA, clock/power gating, CDC, lint
  • Demonstrated collaboration with DV, PD, and DFT across the full RTL2GDS flow to tapeout
  • Scripting (Python/Tcl/) for design automation
  • (Optional) AI/ML accelerator or high-performance compute-datapath design; low-power techniques (UPF); high-speed interfaces (HBM, PCIe, SerDes); advanced nodes (7nm or better); RISC-V/CPU design; FPGA prototyping
Compensation

Final offers depend on level, location, and skills relevant to the role. Additional compensation: equity grant per company guidelines; medical / dental / vision; 401(k); standard PTO. 

Visa Sponsorship

DensityAI sponsors qualified candidates for H-1B, O-1, TN, E-3, and other employment-based visas, and we welcome applicants on F-1 OPT and STEM-OPT. Work authorization is required at start; we provide immigration support to secure or transfer status.

Export Controls

Aspects of this role may involve access to information subject to U.S. export controls (EAR/ITAR). We may discuss licensing or scope adjustments during the interview.

Equal Opportunity

DensityAI is an Equal Opportunity Employer. We do not discriminate on the basis of race, color, religious creed, national origin, ancestry, physical or mental disability, medical condition, genetic information, marital status, sex, gender, gender identity, gender expression, age (40+), sexual orientation, military or veteran status, pregnancy, or any other status protected by law. We comply with the California CROWN Act and provide reasonable accommodations on request.

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