ASIC Engineer
San Jose, CA · On-site
$194K/yr
Emergent technology staffing (UI/UX developers & designers, Mobility & Cloud Engineers, Big Data ... Should have 2-5 years of experience in FPGA/ASIC Development Build RTL designs of digital circuits ...
ASIC Engineer
San Jose, CA · On-site
$194K/yr
Emergent technology staffing (UI/UX developers & designers, Mobility & Cloud Engineers, Big Data ... Should have 2-5 years of experience in FPGA/ASIC Development Build RTL designs of digital circuits ...
ASIC Design Engineer - Networking/ DPU/ AI Systems
Santa Clara, CA · On-site
$180 - $240/hr
Contribute across the full ASIC development lifecycle * Architecture definition * Microarchitecture and RTL design * Design reviews * Implementation support * Tapeout * Silicon bring‑up
ASIC Design Engineer - Networking/ DPU/ AI Systems
Santa Clara, CA · On-site
$180 - $240/hr
Contribute across the full ASIC development lifecycle * Architecture definition * Microarchitecture and RTL design * Design reviews * Implementation support * Tapeout * Silicon bring‑up
We are seeking a Senior ASIC Design Engineer with seasoned experience in the development of high-speed, complex ASICs. The ideal candidate has hands-on experience across the full ASIC development ...
We are seeking a Senior ASIC Design Engineer with seasoned experience in the development of high-speed, complex ASICs. The ideal candidate has hands-on experience across the full ASIC development ...
ASIC Design Engineer - Networking/ DPU/ AI Systems
Santa Clara, CA · On-site
$175K/yr
We are seeking a Senior ASIC Design Engineer with seasoned experience in the development of high-speed, complex ASICs. The ideal candidate has hands-on experience across the full ASIC development ...
ASIC Design Engineer - Networking/ DPU/ AI Systems
Santa Clara, CA · On-site
$175K/yr
We are seeking a Senior ASIC Design Engineer with seasoned experience in the development of high-speed, complex ASICs. The ideal candidate has hands-on experience across the full ASIC development ...
ASIC Engineer 5, 5219
$98.12 - $107.21/hr
ASIC Engineer 5 Duties ... Oversees definition, design, verification, and documentation for ASIC development. * Determines ...
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ASIC Engineer 5, 5219
$98.12 - $107.21/hr
ASIC Engineer 5 Duties ... Oversees definition, design, verification, and documentation for ASIC development. * Determines ...
Principal ASIC Test Development Engineer This role has been designed as 'Hybrid' with an expectation that you will work on average 2 days per week from an HPE office. Who We Are: Hewlett Packard ...
Principal ASIC Test Development Engineer This role has been designed as 'Hybrid' with an expectation that you will work on average 2 days per week from an HPE office. Who We Are: Hewlett Packard ...
Principal ASIC Test Development Engineer This role has been designed as 'Hybrid' with an expectation that you will work on average 2 days per week from an HPE office. Who We Are: Hewlett Packard ...
Principal ASIC Test Development Engineer This role has been designed as 'Hybrid' with an expectation that you will work on average 2 days per week from an HPE office. Who We Are: Hewlett Packard ...
Principal ASIC Test Development Engineer This role has been designed as 'Hybrid' with an expectation that you will work on average 2 days per week from an HPE office. Who We Are: Hewlett Packard ...
Principal ASIC Test Development Engineer This role has been designed as 'Hybrid' with an expectation that you will work on average 2 days per week from an HPE office. Who We Are: Hewlett Packard ...
Principal ASIC Test Development Engineer
Sunnyvale, CA · On-site
$150 - $200/hr
Development of innovative DFT IP in collaboration with cross-functional teams inside and outside the company* Work closely with component engineers to resolve high DPPM ASIC issues at EMS partner ...
Principal ASIC Test Development Engineer
Sunnyvale, CA · On-site
$150 - $200/hr
Development of innovative DFT IP in collaboration with cross-functional teams inside and outside the company* Work closely with component engineers to resolve high DPPM ASIC issues at EMS partner ...
Principal ASIC Test Development Engineer This role has been designed as 'Hybrid' with an expectation that you will work on average 2 days per week from an HPE office. Who We Are: Hewlett Packard ...
Principal ASIC Test Development Engineer This role has been designed as 'Hybrid' with an expectation that you will work on average 2 days per week from an HPE office. Who We Are: Hewlett Packard ...
As an ASIC Engineer specializing in architecture, performance and modeling, you will define and ... ASICs, including development of cycle-accurate and transaction-level simulation environments
As an ASIC Engineer specializing in architecture, performance and modeling, you will define and ... ASICs, including development of cycle-accurate and transaction-level simulation environments
As an ASIC Engineer specializing in architecture, performance and modeling, you will define and ... ASICs, including development of cycle-accurate and transaction-level simulation environments
As an ASIC Engineer specializing in architecture, performance and modeling, you will define and ... ASICs, including development of cycle-accurate and transaction-level simulation environments
As an ASIC Engineer specializing in performance and modeling, you will define and drive the ... development of cycle-accurate and transaction-level simulation environments * Drive ...
As an ASIC Engineer specializing in performance and modeling, you will define and drive the ... development of cycle-accurate and transaction-level simulation environments * Drive ...
ASIC Engineer, Power
Sunnyvale, CA · On-site +1
$146K/yr
As an ASIC Engineer specializing in power on the EDA Infrastructure team, you will develop and ... Evaluate and integrate commercial and internally developed EDA tools into the power analysis flow ...
ASIC Engineer, Power
Sunnyvale, CA · On-site +1
$146K/yr
As an ASIC Engineer specializing in power on the EDA Infrastructure team, you will develop and ... Evaluate and integrate commercial and internally developed EDA tools into the power analysis flow ...
ASIC Engineering Program Manager
San Jose, CA · On-site
$214K - $309K/yr
Because full product development-from design to qualification to production-is within our team, w ... Engineering or other technical field. * Prior experience in managing ASIC design flow (architecture ...
ASIC Engineering Program Manager
San Jose, CA · On-site
$214K - $309K/yr
Because full product development-from design to qualification to production-is within our team, w ... Engineering or other technical field. * Prior experience in managing ASIC design flow (architecture ...
ASIC Engineering Program Manager
San Jose, CA · On-site
$210K - $305K/yr
Because full product development-from design to qualification to production-is within our team, w ... Engineering or other technical field. * Prior experience in managing ASIC design flow (architecture ...
ASIC Engineering Program Manager
San Jose, CA · On-site
$210K - $305K/yr
Because full product development-from design to qualification to production-is within our team, w ... Engineering or other technical field. * Prior experience in managing ASIC design flow (architecture ...
ASIC Engineering Program Manager
San Jose, CA · On-site
$214K - $309K/yr
Because full product development-from design to qualification to production-is within our team, w ... Engineering or other technical field. * Prior experience in managing ASIC design flow (architecture ...
ASIC Engineering Program Manager
San Jose, CA · On-site
$214K - $309K/yr
Because full product development-from design to qualification to production-is within our team, w ... Engineering or other technical field. * Prior experience in managing ASIC design flow (architecture ...
Software Engineering Manager - ASIC Simulation - San Jose, CA
San Jose, CA · On-site
$210K - $305K/yr
This simulator is a critical product that streamlines the development process and significantly ... ASIC development environment, with responsibility for leading and developing engineers
Software Engineering Manager - ASIC Simulation - San Jose, CA
San Jose, CA · On-site
$210K - $305K/yr
This simulator is a critical product that streamlines the development process and significantly ... ASIC development environment, with responsibility for leading and developing engineers
Senior ASIC Design Engineer
Santa Clara, CA · On-site +1
We are looking for a Sr. ASIC Design Engineer! NVIDIA is seeking best-in-class ASIC Design ... We have developed an outstanding team stretching around the globe, whose mission is to push the ...
Senior ASIC Design Engineer
Santa Clara, CA · On-site +1
We are looking for a Sr. ASIC Design Engineer! NVIDIA is seeking best-in-class ASIC Design ... We have developed an outstanding team stretching around the globe, whose mission is to push the ...
Senior ASIC Emulation Engineer
Los Angeles, CA · On-site
$170K - $250K/yr
... co-development and accelerate verification cycles. This is a hands-on role with high ownership ... the ASIC organization. * Work with RTL engineers to compile, map, and optimize designs for ...
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Senior ASIC Emulation Engineer
Los Angeles, CA · On-site
$170K - $250K/yr
... co-development and accelerate verification cycles. This is a hands-on role with high ownership ... the ASIC organization. * Work with RTL engineers to compile, map, and optimize designs for ...
Asic Development Engineer information
What is the difference between Asic Development Engineer vs FPGA Design Engineer?
| Aspect | Asic Development Engineer | FPGA Design Engineer |
|---|---|---|
| Required Credentials | Bachelor's or Master's in Electrical Engineering, VLSI, or related fields; knowledge of ASIC design tools | Bachelor's or Master's in Electrical Engineering, Digital Design; familiarity with FPGA development tools |
| Work Environment | Designing and verifying custom silicon chips in semiconductor labs or R&D centers | Developing and testing FPGA-based solutions in hardware labs or embedded systems environments |
| Industry Usage | Used in semiconductor companies, integrated circuit design firms, and tech giants | Common in telecommunications, aerospace, and embedded systems industries |
While both roles involve digital hardware design, Asic Development Engineers focus on creating custom chips for high-performance applications, whereas FPGA Design Engineers work on programmable hardware solutions. Both require strong digital design skills and familiarity with hardware description languages, but their end products and development environments differ.
What does an ASIC Development Engineer do?
An ASIC Development Engineer designs, develops, and tests application-specific integrated circuits (ASICs) used in electronic devices. They work with hardware description languages like VHDL or Verilog, collaborate with cross-functional teams, and use simulation tools to ensure performance and reliability throughout the development process.
Are ASIC Development Engineers in demand?
ASIC Development Engineers are in high demand due to the growing need for custom hardware solutions in industries like telecommunications, consumer electronics, and automotive. Skills in hardware description languages such as VHDL or Verilog, along with experience in FPGA and ASIC design, increase employability in this specialized field.
What are popular job titles related to Asic Development Engineer jobs in California? For Asic Development Engineer jobs in California, the most frequently searched job titles are:
What job categories do people searching Asic Development Engineer jobs in California look for? The top searched job categories for Asic Development Engineer jobs in California are:
What cities in California are hiring for Asic Development Engineer jobs? Cities in California with the most Asic Development Engineer job openings:
Job description
Company Description
Ideavat provides I.T staffing solutions, enabling companies & jobseekers engage successfully.
With over 20 man years of contingent staffing experience, the management & execution team is committed to provide customized staffing solutions to employers/hiring managers, helping them identify key talents. Emergent technology staffing (UI/UX developers & designers, Mobility & Cloud Engineers, Big Data/Hadoop developers & architects...& more) remains our primary focus!
Job Description
Job Title: ASIC Engineer
Location: San Jose, CA
Duration: 6 Months
Minimum Required Skills:
ASIC Design, FPGA, RTL Design, Chip Architecture, ASIC, Implementation,Synthesis /Conformal (Cadence Tool for formal verification)
Description:
Should have 2-5 years of experience in FPGA/ASIC Development
Build RTL designs of digital circuits using VHDL and System Verilog
Perform frontend design development and integration of large ASIC designs
Collaborate with Chip Architecture, Design Verification, and Physical Design teams to achieve first tapeout success.
Write design documents including high level interface descriptions and design descriptions.
Write function test cases and test benches to verify functionality of designs
Team work and proactive sharing of knowledge
Comfortable working in a fast paced environment.
Qualifications
ASIC Design, FPGA, RTL Design, Chip Architecture, ASIC, Implementation,Synthesis /Conformal (Cadence Tool for formal verification)
Additional Information
All your information will be kept confidential according to EEO guidelines.
About Jobsbridge Institute
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Josbridge Institute is your one-stop destination for your Data, Cloud and Analytics learning needs, powered by Microsoft AI & Cloud platform. We offer a wide range of courses and programs, from foundational to advanced focusing on Data Analysis, Cloud Engg, AI-ML required for Microsoft certification. Our courses are designed to equip you with the practical skills and knowledge required for success in the field of cloud computing, AI and Data Analytics. With our experienced faculty, applied learning and comprehensive curriculum, we are committed to helping you achieve your career goals. Students seeking Internship (CPT & OPT) may apply.
Industry
Business schools and computer and management training
Company size
11 - 50 Employees
Headquarters location
Campbell, CA, US
Year founded
2022