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Volunteer Rtl Verification Jobs in California (NOW HIRING)

Persimmons

RTL / Physical Design Engineer

San Jose, CA

$159K - $164K/yr

Collaborate closely with RTL design, DFT, and verification teams to manage frontend-to-backend ... deemed voluntary and shall not create any express or implied obligation on the part of the ...

Persimmons

RTL / Physical Design Engineer

San Jose, CA · On-site

$159K - $164K/yr

Collaborate closely with RTL design, DFT, and verification teams to manage frontend-to-backend ... deemed voluntary and shall not create any express or implied obligation on the part of the ...

SambaNova

Design Verification Engineer

San Jose, CA · On-site

$120K - $200K/yr

You'll build SystemVerilog and UVM verification environments alongside architects, RTL designers ... We also offer Dental, Vision, Short/Long term Disability, Basic Life, Voluntary Life, and AD&D ...

Actalent

Fpga Engineer

Irvine, CA · On-site

$80 - $110/hr

... FPGA RTL architecture, development, and verification. Job Type & Location This is a Contract ... Life Insurance (Voluntary Life & AD&D for the employee and dependents) * Short and long-term ...

Cisco Systems, Inc.

ASIC DFT Technical Leader

San Jose, CA · On-site

$210.60 - $305.10/hr

Prior experience on hardware design specifications and verification plan/matrix, RTL & testbench ... Optional 10 paid days per full calendar year to volunteer For non‑sales roles, employees are also ...

SK hynix America

AI System Engineer

San Jose, CA · On-site

$117K - $160K/yr

... RTL logic design, verification, and FPGA prototypes * Develop and maintain hardware specifications ... Donation Matching and volunteering opportunities * Corporate discount programs * Free Breakfast ...

SK hynix America

AI System Engineer

San Jose, CA · On-site

$117K - $160K/yr

... RTL logic design, verification, and FPGA prototypes * Develop and maintain hardware specifications ... Donation Matching and volunteering opportunities * Corporate discount programs * Free Breakfast ...

SK hynix America

HBM Logic Architect

San Jose, CA

Develop and verify RTL designs using industry-standard design methodologies. * Provide design ... Donation Matching and volunteering opportunities * Corporate discount programs * Free Breakfast ...

Syntiant

Digital Design Engineer

San Diego, CA · On-site

$190K - $240K/yr

... RTL-to-GDS flow. * Define the digital verification plan. * Verify the digital system and blocks in ... A company-provided Employee Assistance Program (EAP), as well as access to additional voluntary ...

Syntiant

Digital Design Engineer

San Diego, CA · On-site

$190K - $240K/yr

... RTL-to-GDS flow. * Define the digital verification plan. * Verify the digital system and blocks in ... A company-provided Employee Assistance Program (EAP), as well as access to additional voluntary ...

Syntiant

Digital Design Engineer

San Diego, CA · On-site

$190K - $240K/yr

... RTL-to-GDS flow. * Define the digital verification plan. * Verify the digital system and blocks in ... A company-provided Employee Assistance Program (EAP), as well as access to additional voluntary ...

SK hynix America

HBM Logic Architect

San Jose, CA · On-site

$150K - $320K/yr

Develop and verify RTL designs using industry-standard design methodologies. * Provide design ... Donation Matching and volunteering opportunities * Corporate discount programs * Free Breakfast ...

SK hynix America

AI Memory Solution Architect

San Jose, CA · On-site

$73.75 - $97.25/hr

... RTL logic design, verification and FPGA prototypes * Optimize memory system architecture for ... Donation Matching and volunteering opportunities * Corporate discount programs * Free Breakfast ...

SK hynix America

AI Memory Solution Architect

San Jose, CA · On-site

$73.75 - $97.25/hr

... RTL logic design, verification and FPGA prototypes * Optimize memory system architecture for ... Donation Matching and volunteering opportunities * Corporate discount programs * Free Breakfast ...

Cisco

ASIC DFT Technical Leader - CDC

San Jose, CA

$186K - $267K/yr

Define, design and verify ASIC and ASIC subsystems to be deployed in a range of Cisco platforms ... Prior experience with RTL development skills and experiences * Prior experience with CDC/RDC ...

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Volunteer Rtl Verification information

What is the difference between Volunteer RTL Verification vs Test Engineer?

AspectVolunteer RTL VerificationTest Engineer
Required CredentialsBasic understanding of digital design, HDL knowledgeEngineering degree, testing certifications often preferred
Work EnvironmentVolunteer or internship settings, collaborative teamsCorporate or manufacturing environments, structured processes
Industry UsageSemiconductor, electronics, hardware developmentElectronics, software, hardware testing across industries
Common Search/ComparisonYesYes

Volunteer RTL Verification focuses on assisting with digital design testing in a volunteer or internship capacity, often requiring HDL knowledge. Test Engineers typically hold engineering degrees and work in structured environments, performing comprehensive testing of hardware or software products. While both roles involve verification, Volunteer RTL Verification is more entry-level and volunteer-based, whereas Test Engineers are full-time professionals with formal credentials.

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The most popular types of Rtl Verification jobs in California are:

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For Volunteer Rtl Verification jobs in California, the most frequently searched job titles are:

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Cities in California with the most Volunteer Rtl Verification job openings:

Volunteer Rtl Verification jobs near you
Infographic showing various Volunteer Rtl Verification job openings in California as of August 2026, with employment types broken down into 1% As Needed, 85% Full Time, 11% Part Time, 2% Contract, and 1% Nights. Highlights an 89% Physical, 3% Hybrid, and 8% Remote job distribution.

RTL / Physical Design Engineer

Persimmons

San Jose, CA

$159K - $164K/yr

Full-time

Retirement, PTO

Re-posted 7 days ago

Job description

Who we are:

Persimmons is building the infrastructure that will power the next decade of AI. Founded in 2023 by veteran technologists from the worlds of semiconductors, AI systems, and software innovation, We're on a mission to enable smarter devices, more sustainable data centers, and entirely new applications the world hasn't imagined yet.

Why join us:

We're growing fast and looking for bold thinkers, builders, and curious problem-solvers who want to push the limits of AI hardware and software. If you're ready to join a world-class team and play a critical role in making a global impact - we want to talk to you.

What you'll do:

As a Persimmons RTL to PD Engineer, you will be responsible for high quality RTL drops to our PD Partners of next-generation AI silicon. Your primary duties and responsibilities include:

  • Own RTL-to-PD handoff flows to PD Partners, including synthesis, timing constraints, upf and static checks. Ensuring designs meet quality, performance, power & area targets.
  • Drive timing closure by authoring precise timing constraints from RTL understanding, running static timing analysis & resolving setup violations across complex multi-corner environments.
  • Execute floorplanning and physical implementation using Cadence/Synopsys tools, making informed decisions on macro placement & tool options to optimize PPA.
  • Build and maintain scripted, automated design flows that streamline synthesis, analysis, and sign-off processes-leveraging AI agents and modern automation tools to accelerate iteration and reduce manual overhead.
  • Collaborate closely with RTL design, DFT, and verification teams to manage frontend-to-backend handoffs, enforce quality checks, and ensure seamless integration across the design hierarchy.
  • Contribute to advanced post DV design activities including power analysis, CDC/RDC checks, UPF creation, formal verification, and DFT scan and MBIST integration as scope demands.

Requirements

What You Bring To The Table:

  • Educational Foundation: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical discipline.
  • Proven Experience: 3+ years of hands-on RTL-to-PD implementation experience, with demonstrated success taking designs from synthesis through tapeout on real silicon.
  • Technical Mastery: Proficiency in SystemVerilog/Verilog and deep familiarity with Cadence and/or Synopsys synthesis and physical implementation toolchains, including all associated quality and sign-off checks.
  • Specialized Expertise: Strong command of static timing analysis and the ability to write timing constraints from scratch based on RTL-level design understanding.
  • Flow Innovation: Experience developing and maintaining scripted, automated design flows; exposure to AI-assisted automation tools is a strong plus.
  • Demonstrated fluency with modern AI tools and workflows (e.g., leveraging AI assistants for research, analysis, or productivity).

Benefits

  • Competitive salary and benefits package
  • Flexible PTO
  • 401k

Please note: Our organization does not accept unsolicited candidate submissions from external recruiters or agencies. Any such submissions, regardless of form (including but not limited to email, direct messaging, or social media), shall be deemed voluntary and shall not create any express or implied obligation on the part of the organization to pay any fees, commissions, or other compensation. Direct contact of employees, officers, or board members regarding employment opportunities is strictly prohibited and will not receive a response.

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