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Volunteer Rtl Verification Jobs (NOW HIRING)

Persimmons

RTL / Physical Design Engineer

San Jose, CA

$159.40K - $164.10K/yr

Collaborate closely with RTL design, DFT, and verification teams to manage frontend-to-backend ... deemed voluntary and shall not create any express or implied obligation on the part of the ...

Persimmons

RTL / Physical Design Engineer

San Jose, CA · On-site

$159.40K - $164.10K/yr

Collaborate closely with RTL design, DFT, and verification teams to manage frontend-to-backend ... deemed voluntary and shall not create any express or implied obligation on the part of the ...

Neurophos Inc

Lead FPGA Design Engineer

Austin, TX · On-site

$215K - $250K/yr

... RTL verification and software development. * Adapt and implement complex ASIC RTL onto FPGA targets ... Full suite of voluntary benefits, including Dental, Vision, Life, Hospital, Critical Illness, and ...

Silabs

Digital Verification Engineer I

Austin, TX · Hybrid

$84K - $156K/yr

Prior internship or project experience related to verification, RTL development, or semiconductor ... Flexible PTO schedule * 3 paid volunteer days per year * Tuition reimbursement * Free downtown ...

Silicon Labs

Digital Verification Engineer I

Austin, TX · On-site

$84K - $156K/yr

Prior internship or project experience related to verification, RTL development, or semiconductor ... Flexible PTO schedule * 3 paid volunteer days per year * Tuition reimbursement * Free downtown ...

Actalent

FPGA Engineer

Middletown, RI · Hybrid

$60 - $80/hr

... RTL design through verification, integration, and lab validation. You will work hands-on with ... Insurance (Voluntary Life & AD&D for the employee and dependents) • Short and long-term ...

New

Kyocera

Staff Digital Design Engineer

San Diego, CA · On-site

$139K - $232.18K/yr

Paid time off to volunteer * Flexible schedules Work-Life Balance & Culture * Onsite gyms, walking ... QUALIFICATIONS RTL design using SystemVerilog (or Verilog) Simulation, debugging, and verification ...

Kyocera

Staff Digital Design Engineer

San Diego, CA · On-site

$139K - $232.18K/yr

Paid time off to volunteer * Flexible schedules Work-Life Balance & Culture * Onsite gyms, walking ... QUALIFICATIONS RTL design using SystemVerilog (or Verilog) Simulation, debugging, and verification ...

Marvell

Senior Staff Engineer, Physical Design

Burlington, VT · On-site

$136.50K - $140.50K/yr

... physical verification) using industry standard EDA tools * Work with RTL design teams to drive ... off to volunteer. Have a question about our benefits packages - health or financial? Ask your ...

Marvell

Senior Staff Engineer, Physical Design

Morrisville, NC · On-site

$127.20K - $131K/yr

... physical verification) using industry standard EDA tools * Work with RTL design teams to drive ... off to volunteer. Have a question about our benefits packages - health or financial? Ask your ...

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Volunteer Rtl Verification information

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$8

$19

$33

How much do volunteer rtl verification jobs pay per hour?

As of May 28, 2026, the average hourly pay for volunteer rtl verification in the United States is $19.14, according to ZipRecruiter salary data. Most workers in this role earn between $14.42 and $20.19 per hour, depending on experience, location, and employer.

What is the difference between Volunteer RTL Verification vs Test Engineer?

AspectVolunteer RTL VerificationTest Engineer
Required CredentialsBasic understanding of digital design, HDL knowledgeEngineering degree, testing certifications often preferred
Work EnvironmentVolunteer or internship settings, collaborative teamsCorporate or manufacturing environments, structured processes
Industry UsageSemiconductor, electronics, hardware developmentElectronics, software, hardware testing across industries
Common Search/ComparisonYesYes

Volunteer RTL Verification focuses on assisting with digital design testing in a volunteer or internship capacity, often requiring HDL knowledge. Test Engineers typically hold engineering degrees and work in structured environments, performing comprehensive testing of hardware or software products. While both roles involve verification, Volunteer RTL Verification is more entry-level and volunteer-based, whereas Test Engineers are full-time professionals with formal credentials.

More about Volunteer Rtl Verification jobs
What cities are hiring for Volunteer Rtl Verification jobs? Cities with the most Volunteer Rtl Verification job openings:
What are the most commonly searched types of Rtl Verification jobs? The most popular types of Rtl Verification jobs are:
What states have the most Volunteer Rtl Verification jobs? States with the most job openings for Volunteer Rtl Verification jobs include:
What job categories do people searching Volunteer Rtl Verification jobs look for? The top searched job categories for Volunteer Rtl Verification jobs are:
Volunteer Rtl Verification jobs near you
Infographic showing various Volunteer Rtl Verification job openings in the United States as of May 2026, with employment types broken down into 80% Full Time, 15% Part Time, 1% Temporary, and 4% Contract. Highlights an 92% Physical, 3% Hybrid, and 5% Remote job distribution, with an average salary of $39,804 per year, or $19.1 per hour.

RTL / Physical Design Engineer

Persimmons

San Jose, CA

$159.40K - $164.10K/yr

Full-time

Retirement, PTO

Posted 10 days ago

Job description

Who we are:

Persimmons is building the infrastructure that will power the next decade of AI. Founded in 2023 by veteran technologists from the worlds of semiconductors, AI systems, and software innovation, We're on a mission to enable smarter devices, more sustainable data centers, and entirely new applications the world hasn't imagined yet.

Why join us:

We're growing fast and looking for bold thinkers, builders, and curious problem-solvers who want to push the limits of AI hardware and software. If you're ready to join a world-class team and play a critical role in making a global impact - we want to talk to you.

What you'll do:

As a Persimmons RTL to PD Engineer, you will be responsible for high quality RTL drops to our PD Partners of next-generation AI silicon. Your primary duties and responsibilities include:

  • Own RTL-to-PD handoff flows to PD Partners, including synthesis, timing constraints, upf and static checks. Ensuring designs meet quality, performance, power & area targets.
  • Drive timing closure by authoring precise timing constraints from RTL understanding, running static timing analysis & resolving setup violations across complex multi-corner environments.
  • Execute floorplanning and physical implementation using Cadence/Synopsys tools, making informed decisions on macro placement & tool options to optimize PPA.
  • Build and maintain scripted, automated design flows that streamline synthesis, analysis, and sign-off processes-leveraging AI agents and modern automation tools to accelerate iteration and reduce manual overhead.
  • Collaborate closely with RTL design, DFT, and verification teams to manage frontend-to-backend handoffs, enforce quality checks, and ensure seamless integration across the design hierarchy.
  • Contribute to advanced post DV design activities including power analysis, CDC/RDC checks, UPF creation, formal verification, and DFT scan and MBIST integration as scope demands.

Requirements

What You Bring To The Table:

  • Educational Foundation: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical discipline.
  • Proven Experience: 3+ years of hands-on RTL-to-PD implementation experience, with demonstrated success taking designs from synthesis through tapeout on real silicon.
  • Technical Mastery: Proficiency in SystemVerilog/Verilog and deep familiarity with Cadence and/or Synopsys synthesis and physical implementation toolchains, including all associated quality and sign-off checks.
  • Specialized Expertise: Strong command of static timing analysis and the ability to write timing constraints from scratch based on RTL-level design understanding.
  • Flow Innovation: Experience developing and maintaining scripted, automated design flows; exposure to AI-assisted automation tools is a strong plus.
  • Demonstrated fluency with modern AI tools and workflows (e.g., leveraging AI assistants for research, analysis, or productivity).

Benefits

  • Competitive salary and benefits package
  • Flexible PTO
  • 401k

Please note: Our organization does not accept unsolicited candidate submissions from external recruiters or agencies. Any such submissions, regardless of form (including but not limited to email, direct messaging, or social media), shall be deemed voluntary and shall not create any express or implied obligation on the part of the organization to pay any fees, commissions, or other compensation. Direct contact of employees, officers, or board members regarding employment opportunities is strictly prohibited and will not receive a response.

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