RTL Intern
San Jose, CA · On-site
Job Summary As an RTL Intern at Etched, you will help design microarchitecture and implement logic ... Familiarity with verification work and writing test benches * Familiarity with physical design ...
RTL Intern
San Jose, CA · On-site
Job Summary As an RTL Intern at Etched, you will help design microarchitecture and implement logic ... Familiarity with verification work and writing test benches * Familiarity with physical design ...
RTL Intern
San Jose, CA · On-site
Job Summary As an RTL Intern at Etched, you will help design microarchitecture and implement logic ... Familiarity with verification work and writing test benches * Familiarity with physical design ...
Quick apply
RTL Intern
San Jose, CA · On-site
Job Summary As an RTL Intern at Etched, you will help design microarchitecture and implement logic ... Familiarity with verification work and writing test benches * Familiarity with physical design ...
As a Design Verification Engineer Intern on the SoC Digital Verification team, you will help ensure ... with RTL, architecture, and validation teams. What We Need * Help develop and maintain ...
As a Design Verification Engineer Intern on the SoC Digital Verification team, you will help ensure ... with RTL, architecture, and validation teams. What We Need * Help develop and maintain ...
As a Design Verification Engineer Intern on the SoC Digital Verification team, you will help ensure ... with RTL, architecture, and validation teams. What We Need * Help develop and maintain ...
As a Design Verification Engineer Intern on the SoC Digital Verification team, you will help ensure ... with RTL, architecture, and validation teams. What We Need * Help develop and maintain ...
SSG Design Engineering Intern (Fall 2026)
San Jose, CA · On-site
$35/hr
... verification hardware. Come be part of this great SSG Team where you can make an impact that is ... It can involve RTL implementation of a specified micro-architecture in System Verilog, simulating ...
SSG Design Engineering Intern (Fall 2026)
San Jose, CA · On-site
$35/hr
... verification hardware. Come be part of this great SSG Team where you can make an impact that is ... It can involve RTL implementation of a specified micro-architecture in System Verilog, simulating ...
SSG Design Engineering Intern (Fall 2026)
San Jose, CA · On-site
$35/hr
... verification hardware. Come be part of this great SSG Team where you can make an impact that is ... It can involve RTL implementation of a specified micro-architecture in System Verilog, simulating ...
SSG Design Engineering Intern (Fall 2026)
San Jose, CA · On-site
$35/hr
... verification hardware. Come be part of this great SSG Team where you can make an impact that is ... It can involve RTL implementation of a specified micro-architecture in System Verilog, simulating ...
SSG Design Engineering Intern (Fall 2026)
San Jose, CA · On-site
$35/hr
... verification hardware. Come be part of this great SSG Team where you can make an impact that is ... It can involve RTL implementation of a specified micro-architecture in System Verilog, simulating ...
SSG Design Engineering Intern (Fall 2026)
San Jose, CA · On-site
$35/hr
... verification hardware. Come be part of this great SSG Team where you can make an impact that is ... It can involve RTL implementation of a specified micro-architecture in System Verilog, simulating ...
Intern - HBM SoC RTL Design Engineer
Folsom, CA · On-site
$38.84 - $50.24/hr
You will work closely with architecture, verification, physical design, firmware, and product teams ... Design and implement RTL for SoC-level blocks and subsystems used in HBM logic die. * Integrate ...
Intern - HBM SoC RTL Design Engineer
Folsom, CA · On-site
$38.84 - $50.24/hr
You will work closely with architecture, verification, physical design, firmware, and product teams ... Design and implement RTL for SoC-level blocks and subsystems used in HBM logic die. * Integrate ...
PD Intern
San Jose, CA · On-site
Job Summary As a Physical Design intern for Etched, you will be responsible for realizing our ... Familiarity with clocking and reset schemes (RTL/PD) * UVM or formal verification experience (DV ...
Quick apply
PD Intern
San Jose, CA · On-site
Job Summary As a Physical Design intern for Etched, you will be responsible for realizing our ... Familiarity with clocking and reset schemes (RTL/PD) * UVM or formal verification experience (DV ...
PD Intern
San Jose, CA · On-site
Job Summary As a Physical Design intern for Etched, you will be responsible for realizing our ... Familiarity with clocking and reset schemes (RTL/PD) * UVM or formal verification experience (DV)
PD Intern
San Jose, CA · On-site
Job Summary As a Physical Design intern for Etched, you will be responsible for realizing our ... Familiarity with clocking and reset schemes (RTL/PD) * UVM or formal verification experience (DV)
CPU Core Performance Verification Intern - CPU/AI Hardware
Austin, TX · On-site
$50 - $70/hr
As a Performance Verification Intern, you will work alongside CPU architects, micro-architects, and ... How performance models, RTL implementations, and debug tools come together in a real chip ...
CPU Core Performance Verification Intern - CPU/AI Hardware
Austin, TX · On-site
$50 - $70/hr
As a Performance Verification Intern, you will work alongside CPU architects, micro-architects, and ... How performance models, RTL implementations, and debug tools come together in a real chip ...
US 2026 Hardware - Digital Intern
San Jose, CA · On-site
$35 - $45/hr
Youll contribute to RTL design, simulations, and performance optimization for real-world AI ... verification Collaborate with digital and software teams to integrate and validate system ...
US 2026 Hardware - Digital Intern
San Jose, CA · On-site
$35 - $45/hr
Youll contribute to RTL design, simulations, and performance optimization for real-world AI ... verification Collaborate with digital and software teams to integrate and validate system ...
US 2026 Hardware - Digital Intern
San Jose, CA · On-site
$35 - $45/hr
You'll contribute to RTL design, simulations, and performance optimization for real-world AI ... verification Collaborate with digital and software teams to integrate and validate system ...
US 2026 Hardware - Digital Intern
San Jose, CA · On-site
$35 - $45/hr
You'll contribute to RTL design, simulations, and performance optimization for real-world AI ... verification Collaborate with digital and software teams to integrate and validate system ...
Intern - HBM SoC RTL Design Engineer
Folsom, CA · On-site
$38.84 - $50.24/hr
You will work closely with architecture, verification, physical design, firmware, and product teams ... Design and implement RTL for SoClevel blocks and subsystems used in HBM logic die. * Integrate ...
Intern - HBM SoC RTL Design Engineer
Folsom, CA · On-site
$38.84 - $50.24/hr
You will work closely with architecture, verification, physical design, firmware, and product teams ... Design and implement RTL for SoClevel blocks and subsystems used in HBM logic die. * Integrate ...
Digital Design Engineer Intern
Duluth, GA · On-site
... Intern at our Duluth / John's Creek Georgia location. In this role, you will contribute to the ... Digital design flows from RTL to synthesis * UVM verification methodology * Software development ...
Digital Design Engineer Intern
Duluth, GA · On-site
... Intern at our Duluth / John's Creek Georgia location. In this role, you will contribute to the ... Digital design flows from RTL to synthesis * UVM verification methodology * Software development ...
DV Intern
San Jose, CA · On-site
Job Summary As aDesign Verification intern, you will ensure the custom IPs powering our chips ... drive to tackle complex verification challenges. You will collaborate with architects, RTL ...
DV Intern
San Jose, CA · On-site
Job Summary As aDesign Verification intern, you will ensure the custom IPs powering our chips ... drive to tackle complex verification challenges. You will collaborate with architects, RTL ...
As a Senior or Graduate Engineering Intern in DRAM Circuit Design, you will work alongside ... Familiarity with RTL design, synthesis, timing closure, verification, and physical design concepts.
As a Senior or Graduate Engineering Intern in DRAM Circuit Design, you will work alongside ... Familiarity with RTL design, synthesis, timing closure, verification, and physical design concepts.
DV Intern
San Jose, CA · On-site
Job Summary As a Design Verification intern, you will ensure the custom IPs powering our chips ... drive to tackle complex verification challenges. You will collaborate with architects, RTL ...
Quick apply
DV Intern
San Jose, CA · On-site
Job Summary As a Design Verification intern, you will ensure the custom IPs powering our chips ... drive to tackle complex verification challenges. You will collaborate with architects, RTL ...
As a Senior or Graduate Engineering Intern in DRAM Circuit Design, you will work alongside ... Familiarity with RTL design, synthesis, timing closure, verification, and physical design concepts.
As a Senior or Graduate Engineering Intern in DRAM Circuit Design, you will work alongside ... Familiarity with RTL design, synthesis, timing closure, verification, and physical design concepts.
CPU Core Performance Verification Intern - CPU/AI Hardware
Austin, TX · On-site
$50 - $70/hr
As a Performance Verification Intern, you will work alongside CPU architects, micro-architects, and ... How performance models, RTL implementations, and debug tools come together in a real chip ...
CPU Core Performance Verification Intern - CPU/AI Hardware
Austin, TX · On-site
$50 - $70/hr
As a Performance Verification Intern, you will work alongside CPU architects, micro-architects, and ... How performance models, RTL implementations, and debug tools come together in a real chip ...
Intern Rtl Verification information
See salary details
$9.13 - $11.65
9% of jobs
$11.65 - $14.16
8% of jobs
$14.81 is the 25th percentile. Wages below this are outliers.
$14.16 - $16.67
28% of jobs
The median wage is $17.34 / hr.
$16.67 - $19.19
16% of jobs
$20.91 is the 75th percentile. Wages above this are outliers.
$19.19 - $21.70
20% of jobs
$21.70 - $24.21
9% of jobs
$24.21 - $26.73
4% of jobs
$26.73 - $29.24
1% of jobs
$29.24 - $31.75
1% of jobs
$31.75 - $34.27
1% of jobs
$34.27 - $36.78
2% of jobs
$9
$19
$36
How much do intern rtl verification jobs pay per hour?
As of Aug 25, 2026, the average hourly pay for intern rtl verification in the United States is $19.38, according to ZipRecruiter salary data. Most workers in this role earn between $14.42 and $21.63 per hour, depending on experience, location, and employer.
What is the difference between Intern Rtl Verification vs Intern Digital Design?
| Aspect | Intern Rtl Verification | Intern Digital Design |
|---|---|---|
| Primary Focus | Verifying RTL code for correctness and functionality | Designing digital circuits and creating RTL code |
| Skills Required | Hardware description languages (Verilog/VHDL), verification methodologies | Digital logic design, HDL coding, schematic capture |
| Work Environment | Verification teams within semiconductor or electronics companies | Design teams in chip or FPGA development firms |
| Common Certifications | Basic knowledge of HDL, verification tools | HDL proficiency, digital design fundamentals |
Intern Rtl Verification and Intern Digital Design roles share foundational knowledge of HDL and work in hardware development environments. However, verification focuses on testing and validating RTL code, while digital design emphasizes creating and implementing the hardware architecture. Both roles are essential in chip development and often overlap in skills and industry usage.
More about Intern Rtl Verification jobs
What are the most commonly searched types of Rtl Verification jobs?
The most popular types of Rtl Verification jobs are:
What job categories do people searching Intern Rtl Verification jobs look for?
The top searched job categories for Intern Rtl Verification jobs are:
Internship
Re-posted 18 days ago
Job description
About Etched
Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.
Job Summary
As an RTL Intern at Etched, you will help design microarchitecture and implement logic in verilog. You will work with cutting-edge machine learning architectures, contribute to RTL block development, and participate in the full design cycle-from microarchitecture discussions to synthesis and timing feedback. You do not necessarily need prior ML/AI hardware experience; just the ability to learn quickly in a fast-paced, high-autonomy environment. We are looking for Fall '26, Spring '27, and Summer '27 interns.
You may be a good fit if you have
Strong candidates may also have experience with
We encourage you to apply even if you do not believe you meet every single qualification.
Program details
For any questions, contact internships@etched.com
How we're different
Etched believes in the Bitter Lesson. We are the first inference-focused frontier AI system. Our addressable market is the entirety of inference, unlike many of our competitors.
We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.
Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.
Job Summary
As an RTL Intern at Etched, you will help design microarchitecture and implement logic in verilog. You will work with cutting-edge machine learning architectures, contribute to RTL block development, and participate in the full design cycle-from microarchitecture discussions to synthesis and timing feedback. You do not necessarily need prior ML/AI hardware experience; just the ability to learn quickly in a fast-paced, high-autonomy environment. We are looking for Fall '26, Spring '27, and Summer '27 interns.
You may be a good fit if you have
- Progress towards a Bachelor's, Master's, or PhD degree in electrical engineering, computer engineering, or a related field.
- Familiarity with high-speed digital logic
- Exposure to ASIC or SoC design concepts
- Familiarity with SystemVerilog, UVM, or Python
- Familiarity with verification work and writing test benches
- Familiarity with physical design flows and tooling
- Are able to learn quickly about transformers and other aspects of modern artificial intelligence
Strong candidates may also have experience with
- Familiarity with modern ML and LLM model architectures
- Familiarity with numerical representations and functions
- Familiarity with clocking and reset schemes
- Ability to program with Python or another scripting language
We encourage you to apply even if you do not believe you meet every single qualification.
Program details
- 12-week paid internship
- Generous housing support for those relocating
- Daily lunch and dinner in our office
- Based at our office in San Jose, CA
- Direct mentorship from industry leaders and world-class engineers
- Opportunity to work on one of the most important problems of our time
For any questions, contact internships@etched.com
How we're different
Etched believes in the Bitter Lesson. We are the first inference-focused frontier AI system. Our addressable market is the entirety of inference, unlike many of our competitors.
We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.