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Intern Rtl Verification Jobs (NOW HIRING)

Etched

RTL Intern

San Jose, CA · On-site

Job Summary As an RTL Intern at Etched, you will help design microarchitecture and implement logic ... Familiarity with verification work and writing test benches * Familiarity with physical design ...

Etched

RTL Intern

San Jose, CA · On-site

Job Summary As an RTL Intern at Etched, you will help design microarchitecture and implement logic ... Familiarity with verification work and writing test benches * Familiarity with physical design ...

Etched

PD Intern

San Jose, CA · On-site

Job Summary As a Physical Design intern for Etched, you will be responsible for realizing our ... Familiarity with clocking and reset schemes (RTL/PD) * UVM or formal verification experience (DV)

Etched

PD Intern

San Jose, CA · On-site

Job Summary As a Physical Design intern for Etched, you will be responsible for realizing our ... Familiarity with clocking and reset schemes (RTL/PD) * UVM or formal verification experience (DV ...

Astranis

FPGA Intern (Fall 2026)

San Francisco, CA · On-site

$29/hr

RTL Development for FPGA targeted applications * Work with multiple FPGAs and toolchains ... Experience with UVM and advanced SystemVerilog verification * Experience with Xilinx FPGAs

Etched

DV Intern

San Jose, CA · On-site

Job Summary As aDesign Verification intern, you will ensure the custom IPs powering our chips ... drive to tackle complex verification challenges. You will collaborate with architects, RTL ...

Etched

DV Intern

San Jose, CA · On-site

Job Summary As a Design Verification intern, you will ensure the custom IPs powering our chips ... drive to tackle complex verification challenges. You will collaborate with architects, RTL ...

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Intern Rtl Verification information

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How much do intern rtl verification jobs pay per hour?

As of Jul 14, 2026, the average hourly pay for intern rtl verification in the United States is $19.38, according to ZipRecruiter salary data. Most workers in this role earn between $14.42 and $21.63 per hour, depending on experience, location, and employer.

What is the difference between Intern Rtl Verification vs Intern Digital Design?

AspectIntern Rtl VerificationIntern Digital Design
Primary FocusVerifying RTL code for correctness and functionalityDesigning digital circuits and creating RTL code
Skills RequiredHardware description languages (Verilog/VHDL), verification methodologiesDigital logic design, HDL coding, schematic capture
Work EnvironmentVerification teams within semiconductor or electronics companiesDesign teams in chip or FPGA development firms
Common CertificationsBasic knowledge of HDL, verification toolsHDL proficiency, digital design fundamentals

Intern Rtl Verification and Intern Digital Design roles share foundational knowledge of HDL and work in hardware development environments. However, verification focuses on testing and validating RTL code, while digital design emphasizes creating and implementing the hardware architecture. Both roles are essential in chip development and often overlap in skills and industry usage.

More about Intern Rtl Verification jobs
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Intern Rtl Verification jobs near you
Infographic showing various Intern Rtl Verification job openings in the United States as of July 2026, with employment types broken down into 18% Internship, 1% As Needed, 50% Full Time, 28% Part Time, 2% Temporary, and 1% Contract. Highlights an 94% Physical, 2% Hybrid, and 4% Remote job distribution, with an average salary of $40,304 per year, or $19.4 per hour.

RTL Intern

Etched

San Jose, CA • On-site

Internship

Posted 6 days ago

Job description

About Etched
Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.
Job Summary
As an RTL Intern at Etched, you will help design microarchitecture and implement logic in verilog. You will work with cutting-edge machine learning architectures, contribute to RTL block development, and participate in the full design cycle-from microarchitecture discussions to synthesis and timing feedback. You do not necessarily need prior ML/AI hardware experience; just the ability to learn quickly in a fast-paced, high-autonomy environment. We are looking for Fall '26, Spring '27, and Summer '27 interns.
You may be a good fit if you have
  • Progress towards a Bachelor's, Master's, or PhD degree in electrical engineering, computer engineering, or a related field.
  • Familiarity with high-speed digital logic
  • Exposure to ASIC or SoC design concepts
  • Familiarity with SystemVerilog, UVM, or Python
  • Familiarity with verification work and writing test benches
  • Familiarity with physical design flows and tooling
  • Are able to learn quickly about transformers and other aspects of modern artificial intelligence

Strong candidates may also have experience with
  • Familiarity with modern ML and LLM model architectures
  • Familiarity with numerical representations and functions
  • Familiarity with clocking and reset schemes
  • Ability to program with Python or another scripting language

We encourage you to apply even if you do not believe you meet every single qualification.
Program details
  • 12-week paid internship
  • Generous housing support for those relocating
  • Daily lunch and dinner in our office
  • Based at our office in San Jose, CA
  • Direct mentorship from industry leaders and world-class engineers
  • Opportunity to work on one of the most important problems of our time

For any questions, contact internships@etched.com
How we're different
Etched believes in the Bitter Lesson. We are the first inference-focused frontier AI system, betting early on transformer and transformer-like architectures and on increasing model sizes. Our addressable market is the entirety of inference, unlike many of our competitors.
We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.

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