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Contractual Rtl Verification Jobs (NOW HIRING)

Google

CPU SoC Verification Engineer

San Diego, CA · On-site

$144K/yr

Experience in RTL verification and Gate Level Simulation (GLS) workflows. Preferred qualifications ... Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not ...

Google Inc.

CPU SoC Verification Engineer

Mountain View, CA · On-site

$138 - $197/hr

Experience in RTL verification and Gate Level Simulation (GLS) workflows. Preferred qualifications ... Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not ...

Google Inc.

RTL Design Engineer, TPU

Sunnyvale, CA · On-site

$163 - $237/hr

Leverage design and verification expertise to verify complex digital designs, focusing on TPU ... Alphabet Inc. is your sole contractual partner with respect to equity grants. Google is proud to be ...

Google

Senior CPU RTL Design Engineer

Mountain View, CA · On-site

Partner with verification, power, and physical design teams to ensure designs meet area, power, and ... Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not ...

Google

RTL Design Engineer, Silicon

Mountain View, CA · On-site

Knowledge of ASIC Verification or DFT. About the job Be part of a team that pushes boundaries ... Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not ...

Google

Senior Design Engineer, RTL

Mountain View, CA · On-site

Knowledge of ASIC Verification, DFT, synthesis, STA, or physical design. * Knowledge of FPGA and ... Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not ...

Google

CPU Emulation Engineer, Silicon

Austin, TX · On-site

Experience in RTL design using Verilog or SystemVerilog. * Experience writing scripts or developing ... Experience collaborating with cross-functional design verification (DV) and silicon design teams.

Google

TPU Design Engineer, Silicon

Mountain View, CA · On-site

Experience with logic synthesis techniques to optimize RTL code, performance and power as well as ... Engage with Verification and Silicon Validation teams to ensure functionality of the design

Google Inc.

Physical Design Lead, ASIC

Sunnyvale, CA · On-site

$192 - $279/hr

... RTL to GDSII, and manage the full physical design flow. You'll be responsible for detailed ... Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not ...

FishEye Software

FPGA Engineer

Tewksbury, MA · On-site

$80K - $190K/yr

Perform design verification using self-checking methods, directed and constrained random testing ... Experience with RTL simulation tools (Questasim) * Familiarity with advanced FPGA platforms (MPSoC ...

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How much do contractual rtl verification jobs pay per year?

As of Sep 6, 2026, the average yearly pay for contractual rtl verification in the United States is $156,077.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $175,500.00 per year, depending on experience, location, and employer.

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Contractual Rtl Verification jobs near you

CPU SoC Verification Engineer

Google

San Diego, CA • On-site

$144K/yr

Full-time

Re-posted 23 hours ago

Google rating

8.8

Company rating: 8.8 out of 10

Based on 103 frontline employees who took The Breakroom Quiz

48th of 247 rated software companies

Job description

info_outline
X In most instances, this position requires in-person interviews as part of the hiring process.
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: San Diego, CA, USA; Mountain View, CA, USA.
Minimum qualifications:
  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
  • 4 years of experience with ARM-based SoC verification, including cache coherency, Network-on-Chip (NoC) interconnects, or high-speed bus protocols.
  • Experience with post-silicon debug and diagnosing failures across Process, Voltage, and Temperature (PVT) corners.
  • Experience in RTL verification and Gate Level Simulation (GLS) workflows.

Preferred qualifications:
  • Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  • Experience with UVM/OVM methodologies and using Python or Perl to automate ARM SoC verification flows.

About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a CPU SoC DV Engineer, you will be responsible for ensuring the functional integrity of CPU subsystems from initial RTL simulation through to final silicon characterization. You will develop robust verification environments, drive GLS, and partner with ATE teams to debug and stabilize high-speed patterns in a production environment.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $138000 - $197000 (USD) 15% bonus target equity benefits
Learn more about benefits at Google .
Responsibilities
  • Drive ARM SoC and sub-system level verification, simulation, and debug for CPU RTL and gate-level netlists.
  • Lead post-silicon debug efforts to diagnose complex hardware failures and ensure pattern stability in production.
  • Translate simulation-based functional sequences into ATE/SLT-ready formats, ensuring high-fidelity pattern conversion through virtual tester environments.
  • Execute GLS and timing-annotated (SDF) simulations using industry-standard EDA tools.
  • Generate and convert ATE patterns utilizing virtual tester environments to ensure high-fidelity translation from simulation.

Information collected and processed as part of your Google Careers profile, and any job applications you choose to submit is subject to Google's Applicant and Candidate Privacy Policy .
Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire .
If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form .
Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.
To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees, or any other organization location. Google is not responsible for any fees related to unsolicited resumes.
Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.

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