S.-based customers, covering RTL design to implementation. * Conduct foundry verification of ... Donation Matching and volunteering opportunities * Corporate discount programs * Free Breakfast ...
S.-based customers, covering RTL design to implementation. * Conduct foundry verification of ... Donation Matching and volunteering opportunities * Corporate discount programs * Free Breakfast ...
Senior Technical Recruiter - Hardware
Austin, TX · On-site
$170K - $230K/yr
Own full lifecycle recruiting for hardware roles across Design Verification, ASIC/RTL design ... We also offer Dental, Vision, Short/Long term Disability, Basic Life, Voluntary Life, and AD&D ...
Senior Technical Recruiter - Hardware
Austin, TX · On-site
$170K - $230K/yr
Own full lifecycle recruiting for hardware roles across Design Verification, ASIC/RTL design ... We also offer Dental, Vision, Short/Long term Disability, Basic Life, Voluntary Life, and AD&D ...
HBM Logic Architect
San Jose, CA · On-site
$150K - $320K/yr
Develop and verify RTL designs using industry-standard design methodologies. * Provide design ... Donation Matching and volunteering opportunities * Corporate discount programs * Free Breakfast ...
HBM Logic Architect
San Jose, CA · On-site
$150K - $320K/yr
Develop and verify RTL designs using industry-standard design methodologies. * Provide design ... Donation Matching and volunteering opportunities * Corporate discount programs * Free Breakfast ...
AI System Engineer
San Jose, CA · On-site
$155K - $215K/yr
... RTL logic design, verification, and FPGA prototypes * Develop and maintain hardware specifications ... Donation Matching and volunteering opportunities * Corporate discount programs * Free Breakfast ...
AI System Engineer
San Jose, CA · On-site
$155K - $215K/yr
... RTL logic design, verification, and FPGA prototypes * Develop and maintain hardware specifications ... Donation Matching and volunteering opportunities * Corporate discount programs * Free Breakfast ...
AI Memory Solution Architect
San Jose, CA · On-site
$73.75 - $97.25/hr
... RTL logic design, verification and FPGA prototypes * Optimize memory system architecture for ... Donation Matching and volunteering opportunities * Corporate discount programs * Free Breakfast ...
AI Memory Solution Architect
San Jose, CA · On-site
$73.75 - $97.25/hr
... RTL logic design, verification and FPGA prototypes * Optimize memory system architecture for ... Donation Matching and volunteering opportunities * Corporate discount programs * Free Breakfast ...
Digital Design Engineer I
Austin, TX · Hybrid
$78K - $146K/yr
... RTL development and integration. * Collaborate with cross-functional teams, including analog design, verification, firmware, and systems engineers, to deliver high-quality silicon solutions.
Digital Design Engineer I
Austin, TX · Hybrid
$78K - $146K/yr
... RTL development and integration. * Collaborate with cross-functional teams, including analog design, verification, firmware, and systems engineers, to deliver high-quality silicon solutions.
WI · On-site
$124K - $128K/yr
You will define how we take designs from RTL to tapeout on leading-edge nodes, and grow the team ... Own physical verification and IP/library management for the digital design org. * Build and lead a ...
WI · On-site
$124K - $128K/yr
You will define how we take designs from RTL to tapeout on leading-edge nodes, and grow the team ... Own physical verification and IP/library management for the digital design org. * Build and lead a ...
$170K - $230K/yr
Own full lifecycle recruiting for hardware roles across Design Verification, ASIC/RTL design ... We also offer Dental, Vision, Short/Long term Disability, Basic Life, Voluntary Life, and AD&D ...
$170K - $230K/yr
Own full lifecycle recruiting for hardware roles across Design Verification, ASIC/RTL design ... We also offer Dental, Vision, Short/Long term Disability, Basic Life, Voluntary Life, and AD&D ...
AI System Engineer
San Jose, CA · On-site
$155K - $215K/yr
... RTL logic design, verification, and FPGA prototypes * Develop and maintain hardware specifications ... Donation Matching and volunteering opportunities * Corporate discount programs * Free Breakfast ...
AI System Engineer
San Jose, CA · On-site
$155K - $215K/yr
... RTL logic design, verification, and FPGA prototypes * Develop and maintain hardware specifications ... Donation Matching and volunteering opportunities * Corporate discount programs * Free Breakfast ...
$100K - $103K/yr
You will define how we take designs from RTL to tapeout on leading-edge nodes, and grow the team ... Own physical verification and IP/library management for the digital design org. * Build and lead a ...
$100K - $103K/yr
You will define how we take designs from RTL to tapeout on leading-edge nodes, and grow the team ... Own physical verification and IP/library management for the digital design org. * Build and lead a ...
Voluntary Vision, Dental, Life, and Disability insurance options * Generous paid vacation, sick ... Hands-on experience with RTL design/verification (SystemVerilog/VHDL), hardware-software co-design ...
Voluntary Vision, Dental, Life, and Disability insurance options * Generous paid vacation, sick ... Hands-on experience with RTL design/verification (SystemVerilog/VHDL), hardware-software co-design ...
Digital Design Engineer I
Austin, TX · On-site
$78K - $146K/yr
... RTL development and integration. * Collaborate with cross-functional teams, including analog design, verification, firmware, and systems engineers, to deliver high-quality silicon solutions.
Digital Design Engineer I
Austin, TX · On-site
$78K - $146K/yr
... RTL development and integration. * Collaborate with cross-functional teams, including analog design, verification, firmware, and systems engineers, to deliver high-quality silicon solutions.
Director of 3D Stacked Logic Design
San Jose, CA · On-site
$250K - $300K/yr
S.-based customers (including RTL design to implementation). * Drive foundry Verification of ... Donation Matching and volunteering opportunities * Corporate discount programs * Free Breakfast ...
Director of 3D Stacked Logic Design
San Jose, CA · On-site
$250K - $300K/yr
S.-based customers (including RTL design to implementation). * Drive foundry Verification of ... Donation Matching and volunteering opportunities * Corporate discount programs * Free Breakfast ...
You'll work closely with System Architects, RTL, physical design, and verification leads to close ... Full suite of voluntary benefits, including Dental, Vision, Life, Hospital, Critical Illness, and ...
You'll work closely with System Architects, RTL, physical design, and verification leads to close ... Full suite of voluntary benefits, including Dental, Vision, Life, Hospital, Critical Illness, and ...
You'll work closely with System Architects, RTL, physical design, and verification leads to close ... Full suite of voluntary benefits, including Dental, Vision, Life, Hospital, Critical Illness, and ...
You'll work closely with System Architects, RTL, physical design, and verification leads to close ... Full suite of voluntary benefits, including Dental, Vision, Life, Hospital, Critical Illness, and ...
Principal SoC Design Engineer / SoC Lead
Austin, TX · On-site
$225K - $300K/yr
You'll work closely with System Architects, RTL, physical design, and verification leads to close ... Full suite of voluntary benefits, including Dental, Vision, Life, Hospital, Critical Illness, and ...
Principal SoC Design Engineer / SoC Lead
Austin, TX · On-site
$225K - $300K/yr
You'll work closely with System Architects, RTL, physical design, and verification leads to close ... Full suite of voluntary benefits, including Dental, Vision, Life, Hospital, Critical Illness, and ...
You'll work closely with System Architects, RTL, physical design, and verification leads to close ... Full suite of voluntary benefits, including Dental, Vision, Life, Hospital, Critical Illness, and ...
You'll work closely with System Architects, RTL, physical design, and verification leads to close ... Full suite of voluntary benefits, including Dental, Vision, Life, Hospital, Critical Illness, and ...
Digital Design Engineer
$190K - $240K/yr
... RTL-to-GDS flow. * Define the digital verification plan. * Verify the digital system and blocks in ... A company-provided Employee Assistance Program (EAP), as well as access to additional voluntary ...
Digital Design Engineer
$190K - $240K/yr
... RTL-to-GDS flow. * Define the digital verification plan. * Verify the digital system and blocks in ... A company-provided Employee Assistance Program (EAP), as well as access to additional voluntary ...
Digital Design Engineer
San Diego, CA · On-site
$190K - $240K/yr
... RTL-to-GDS flow. * Define the digital verification plan. * Verify the digital system and blocks in ... A company-provided Employee Assistance Program (EAP), as well as access to additional voluntary ...
Digital Design Engineer
San Diego, CA · On-site
$190K - $240K/yr
... RTL-to-GDS flow. * Define the digital verification plan. * Verify the digital system and blocks in ... A company-provided Employee Assistance Program (EAP), as well as access to additional voluntary ...
3D Stacked Logic Design Engineer
San Jose, CA · On-site
$150K - $320K/yr
S.-based customers, covering RTL design to implementation. * Conduct foundry verification of ... Donation Matching and volunteering opportunities * Corporate discount programs * Free Breakfast ...
3D Stacked Logic Design Engineer
San Jose, CA · On-site
$150K - $320K/yr
S.-based customers, covering RTL design to implementation. * Conduct foundry verification of ... Donation Matching and volunteering opportunities * Corporate discount programs * Free Breakfast ...
Volunteer Rtl Verification information
See salary details
$8.41 - $10.71
2% of jobs
$10.71 - $13
9% of jobs
$14.63 is the 25th percentile. Wages below this are outliers.
$13 - $15.30
19% of jobs
$15.30 - $17.59
13% of jobs
The median wage is $18.09 / hr.
$17.59 - $19.89
32% of jobs
$19.95 is the 75th percentile. Wages above this are outliers.
$19.89 - $22.18
9% of jobs
$22.18 - $24.48
4% of jobs
$24.48 - $26.77
4% of jobs
$26.77 - $29.06
0% of jobs
$29.06 - $31.36
4% of jobs
$31.36 - $33.65
3% of jobs
$8
$19
$33
How much do volunteer rtl verification jobs pay per hour?
As of Sep 15, 2026, the average hourly pay for volunteer rtl verification in the United States is $19.14, according to ZipRecruiter salary data. Most workers in this role earn between $14.42 and $20.19 per hour, depending on experience, location, and employer.
What is the difference between Volunteer RTL Verification vs Test Engineer?
| Aspect | Volunteer RTL Verification | Test Engineer |
|---|---|---|
| Required Credentials | Basic understanding of digital design, HDL knowledge | Engineering degree, testing certifications often preferred |
| Work Environment | Volunteer or internship settings, collaborative teams | Corporate or manufacturing environments, structured processes |
| Industry Usage | Semiconductor, electronics, hardware development | Electronics, software, hardware testing across industries |
| Common Search/Comparison | Yes | Yes |
Volunteer RTL Verification focuses on assisting with digital design testing in a volunteer or internship capacity, often requiring HDL knowledge. Test Engineers typically hold engineering degrees and work in structured environments, performing comprehensive testing of hardware or software products. While both roles involve verification, Volunteer RTL Verification is more entry-level and volunteer-based, whereas Test Engineers are full-time professionals with formal credentials.
More about Volunteer Rtl Verification jobs
What cities are hiring for Volunteer Rtl Verification jobs?
Cities with the most Volunteer Rtl Verification job openings:
What are the most commonly searched types of Rtl Verification jobs?
The most popular types of Rtl Verification jobs are:
What states have the most Volunteer Rtl Verification jobs?
States with the most job openings for Volunteer Rtl Verification jobs include:
What are popular job titles related to Volunteer Rtl Verification jobs?
For Volunteer Rtl Verification jobs, the most frequently searched job titles are:
3D Stacked Logic Design Engineer
San Jose, CA • On-site
SK hynix America
• Semiconductor and Electronic Component Manufacturing • 201 - 500 employees201 - 500 employees
Full-time
Medical, Retirement, PTO
Re-posted 29 days ago
Job description
Job Title: 3D Stacked Logic Design Engineer
Office Location: San Jose, CA
Job Type: Full-Time
Work Model: Onsite
Job Summary:
To strengthen leadership in the DRAM-on-Logic era through optimized DRAM die design, we are seeking talent capable of driving the co-design of 3D-stacked DRAM logic dies in close collaboration with U.S.-based customers. This strategic hiring initiative aims to enhance our global competitiveness by fostering deep engagement with key American clients, ensuring that our die design solutions are precisely aligned with their evolving technical requirements and market demands.
Responsibilities:
- Strengthen leadership in the DRAM-on-Logic era through advanced digital IP design for 3D-stacked DRAM.
- Provide digital IP services for 3D-stacked DRAM to enable DRAM-on-Logic system configurations for customers.
- Co-design 3D-stacked DRAM Logic Dies with U.S.-based customers.
- Improve competitiveness through close engagement with customers in the U.S.
- Design high-speed digital IP for 3D-stacked DRAM peripheral circuits and DRAM DFT with U.S.-based customers, covering RTL design to implementation.
- Conduct foundry verification of service-ready IPs and setting up infrastructure for the IP business.
- Deliver services to ensure seamless IP integration in customer design environments.
- Design digital logic blocks for 3D-stacked DRAM peripherals and Design-for-Test (DFT) features.
- Establish close technical engagement with key U.S.-based customers to address immediate 3D-stacked DRAM requirements.
- Establish close technical engagement with foundry partners (e.g., TSMC, Intel) to build digital IP for 3D-stacked DRAM.
Qualifications:
- Bachelor's degree or higher in Electrical Engineering or a related discipline with 5+ years of relevant experience.
- Development of Digital Logic IP/SoC based on Hardware Description Languages (Verilog, VHDL).
- Experience in RTL design and implementation memory PHY, hard macro IP for high-speed circuit, or high-speed digital IP design.
- Experience with memory controllers.
- Experience in memory Built-in Self-Test (BIST), DRAM Design for Test (DFT) / Design for Debug (DFD).
- Deep understanding of PPA analysis and optimization, and physical design.
- Excellent verbal and written communication in English; ability to present technical concepts to cross functional teams and senior management.
Benefits:
- Top Tier health insurance at no employee cost
- Paid day offs: Paid Time Off, Company Holidays, Parental Leave, Happy Fridays
- 401k Matching
- Flexible Spending Account (FSA) for Health Care & Dependent Care
- Educational reimbursement up to $10,000 per year
- Donation Matching and volunteering opportunities
- Corporate discount programs
- Free Breakfast/Lunch/Dinner provided to employees
About SK Hynix America
Sourced by ZipRecruiter
Industry
Semiconductor and electronic component manufacturing
Company size
201 - 500 Employees
Headquarters location
San Jose, CA, US
Year founded
1983