Palo Alto, CA (Or potentially Burlington, MA) Length of Contract: 6 months+ (Temp-to-Perm) Ideal ... Background in advanced nodes ( 28nm) and cross-functional collaboration (verification, systems ...
Palo Alto, CA (Or potentially Burlington, MA) Length of Contract: 6 months+ (Temp-to-Perm) Ideal ... Background in advanced nodes ( 28nm) and cross-functional collaboration (verification, systems ...
... 6-9 months - Temp-to-Perm Hours: 40 hours per week Scope: Client needs someone to lead ... Proficiency in SystemVerilog/UVM + RTL design concepts * Experience building self-checking ...
... 6-9 months - Temp-to-Perm Hours: 40 hours per week Scope: Client needs someone to lead ... Proficiency in SystemVerilog/UVM + RTL design concepts * Experience building self-checking ...
Digital IC Design Engineer Intern
Fremont, CA · On-site
$35/hr
Micro-architecture design and RTL implementation of: * Low-power digital signal processors * Low ... Temporary Employees & Interns excluded
Digital IC Design Engineer Intern
Fremont, CA · On-site
$35/hr
Micro-architecture design and RTL implementation of: * Low-power digital signal processors * Low ... Temporary Employees & Interns excluded
Design Verification Intern
Burlingame, CA · On-site
$45 - $60/hr
Coursework or project experience with Computer Architecture, RTL Design, ML systems, or performance ... The hourly rate for this temporary internship position is $45.00/hour to $60.00/hour. The actual ...
Design Verification Intern
Burlingame, CA · On-site
$45 - $60/hr
Coursework or project experience with Computer Architecture, RTL Design, ML systems, or performance ... The hourly rate for this temporary internship position is $45.00/hour to $60.00/hour. The actual ...
Design Verification Intern
$45 - $60/hr
Coursework or project experience with Computer Architecture, RTL Design, ML systems, or performance ... The hourly rate for this temporary internship position is $45.00/hour to $60.00/hour. The actual ...
Design Verification Intern
$45 - $60/hr
Coursework or project experience with Computer Architecture, RTL Design, ML systems, or performance ... The hourly rate for this temporary internship position is $45.00/hour to $60.00/hour. The actual ...
Design Verification Intern
Burlingame, CA · On-site
$45 - $60/hr
Coursework or project experience with Computer Architecture, RTL Design, ML systems, or performance ... The hourly rate for this temporary internship position is $45.00/hour to $60.00/hour. The actual ...
Quick apply
Design Verification Intern
Burlingame, CA · On-site
$45 - $60/hr
Coursework or project experience with Computer Architecture, RTL Design, ML systems, or performance ... The hourly rate for this temporary internship position is $45.00/hour to $60.00/hour. The actual ...
Principal BSP Embedded Software Engineer - Silicon Systems
Bodega Bay, CA · On-site
$164K - $230K/yr
It is approved for a temporary remote work exception while our sites are developed. About the Role ... Support pre-silicon validation using emulation and RTL simulation environments Minimum ...
Principal BSP Embedded Software Engineer - Silicon Systems
Bodega Bay, CA · On-site
$164K - $230K/yr
It is approved for a temporary remote work exception while our sites are developed. About the Role ... Support pre-silicon validation using emulation and RTL simulation environments Minimum ...
Temporary Rtl Verification information
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Job description
Title: ASIC/SoC RTL Design Engineer
Location: Palo Alto, CA (Or potentially Burlington, MA)
Length of Contract: 6 months+ (Temp-to-Perm)
Ideal Start: 6/1/2026
Responsibilities :
Own end-to-end design of complex SoC subsystems, driving architecture, RTL implementation, and tapeout. Focus on high-performance Datapath, PPA optimization, and cross-functional integration across silicon, firmware, and system teams.
Must haves:
- 8 12+ years in ASIC/SoC digital design with hands-on RTL ownership
- Strong SystemVerilog/Verilog RTL development (Datapath, control logic, state machines)
- Proven experience owning subsystems from architecture RTL tapeout
- Deep understanding of PPA tradeoffs, timing closure, clock/reset, and power-aware design
- Experience designing high throughput Datapath (buffering, arbitration, memory hierarchy)
- Background in advanced nodes ( 28nm) and cross-functional collaboration (verification, systems, firmware)
Pluses:
- Experience with compute-intensive pipelines (DSP, AI, beamforming, MAC Datapath)
- Exposure to sensor / imaging systems (e.g., ultrasound, data acquisition)
- Experience with programmable compute blocks (AI accelerators, MPUs, eFPGA)
About Oxford Global Resources
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Oxford Global Resources delivers tailored solutions for any technical challenges you face using our partnership-first approach. We specialize in workforce mobilization, digital transformation, and modern enterprise. We are committed to providing you with The Right Talent. Right Now. In 1984, we started Oxford with a handful of employees in a converted schoolhouse in Reading, Massachusetts. The people that shape our organization are some of the best in the industry. They are dedicated to making an impact and are with you every step of the way. We strive to meet the most pressing needs, solve the most complex problems, and go beyond expectations for our clients and our consultants. Together, we drive great outcomes. Whether you’d like to join the thousands of professionals who trust Oxford to advance their careers or partner with us to solve a challenge your business is facing, contact us at any of our 35 global offices.
Industry
Recruiting and staffing services
Company size
501 - 1,000 Employees
Headquarters location
Beverly, MA, US
Year founded
1984