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Principal Asic Design Engineer Jobs in California

Fusion408

Principal ASIC Design Engineer

Carlsbad, CA · On-site

Principal ASIC Design Engineer Description: Expertise in at least 3 of the following: communication system design, RF radio design, digital ASIC design, applications platforms, and semiconductor ...

Fusion408

Principal ASIC Design Engineer

Carlsbad, CA · On-site

Principal ASIC Design Engineer Description: Expertise in at least 3 of the following: communication system design, RF radio design, digital ASIC design, applications platforms, and semiconductor ...

SpaceX

Principal ASIC Design Engineer (Starshield)

Hawthorne, CA

$200K - $285K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

PRINCIPAL ASIC DESIGN ENGINEER (STARSHIELD) Starshield leverages SpaceX's Starlink technology and launch capability to support national security efforts. While Starlink is designed for consumer and ...

SpaceX

Principal ASIC Design Engineer (Starshield)

Hawthorne, CA · On-site

$200K - $285K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

PRINCIPAL ASIC DESIGN ENGINEER (STARSHIELD) Starshield leverages SpaceX's Starlink technology and launch capability to support national security efforts. While Starlink is designed for consumer and ...

Qualcomm

ASIC Design Engineer

San Diego, CA · On-site

Principal Duties and Responsibilities * Participate in the architecture, design, implementation ... sound ASIC engineering practices. * Participate in design reviews and contribute technical ...

Conductor

ASIC Design Engineer

San Francisco, CA · On-site

$130 - $210/hr

We're looking for ASIC design engineers to contribute to and own blocks in the development of the A-0 and A-1 wafer products, across both the XPU, memory chiplet and other dies on the wafer. Ideal ...

Boeing

Principal ASIC Engineer

El Segundo, CA · On-site

  • Medical

  • Life

  • Retirement

Principal ASIC Engineer Company: The Boeing Company Boeing Space, Intelligence & Weapons Systems ... And we're applying the latest digital IC design processes with industry-best tools to enable ...

Blue Origin

Principal ASIC Design Engineer - Terawave

San Diego, CA · On-site

$269K - $376K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

This role requires a highly skilled Design and Verification Engineer with extensive experience in ... ASIC to/from FPGA flow Minimum Qualifications * BS, MS in Electrical Engineering or a related ...

Broadcom Inc.

Lead ASIC Design Engineer

San Jose, CA · On-site

$143.80 - $230/hr

  • Medical

  • Dental

  • Vision

  • Retirement

  • PTO

Lead ASIC Design EngineerSkip to main content#Lead ASIC Design Engineer page is loaded## Lead ASIC ... We are seeking a hands-on Principal Digital Design Engineer to serve as the **Chip Lead** for our ...

Micron Technology, Inc

Sr. ASIC Design Engineer

San Jose, CA · On-site

$168 - $336/hr

  • Medical

  • Dental

  • Vision

  • PTO

Sr. ASIC Design Engineer Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence. What's Encouraged Daily As ...

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All JobsPrincipal Asic Design Engineer JobsPrincipal Asic Design Engineer Jobs in California

Principal Asic Design Engineer information

What is the difference between Principal Asic Design Engineer vs Senior Asic Design Engineer?

AspectPrincipal Asic Design EngineerSenior Asic Design Engineer
QualificationsBachelor's or Master's in Electrical Engineering or Computer Engineering; extensive ASIC design experienceBachelor's or Master's in Electrical Engineering or Computer Engineering; significant ASIC design experience
Work EnvironmentLeads design projects, mentors teams, collaborates with cross-functional teamsPerforms complex ASIC design tasks, supports project development, collaborates with engineers
ResponsibilitiesArchitects ASIC solutions, oversees design quality, guides junior engineersDesigns ASIC components, reviews work, implements design improvements

The main difference is that the Principal Asic Design Engineer typically leads projects and mentors teams, while the Senior Asic Design Engineer focuses on executing complex design tasks. Both roles require strong ASIC design skills and relevant experience, but the principal level involves more leadership and strategic responsibilities.

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For Principal Asic Design Engineer jobs in California, the most frequently searched job titles are:

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Cities in California with the most Principal Asic Design Engineer job openings:

Principal Asic Design Engineer jobs near you
Infographic showing various Principal Asic Design Engineer job openings in California as of August 2026, with employment types broken down into 100% Full Time. Highlights an 100% In-person job distribution.

Principal ASIC Design Engineer

Fusion408

Carlsbad, CA • On-site

Full-time

Re-posted 19 days ago

Job description

Principal ASIC Design Engineer
Description:
Expertise in at least 3 of the following: communication system design, RF radio design, digital ASIC design, applications platforms, and semiconductor device modeling.
Requirements:
Principal Engineer will be responsible for design and development from multiple ASIC blocks to a complete Core/Chip in communications/digital signal processing (DSP) IC products. These include building blocks/Cores for communication functions. The responsibility includes working with system engineering or product marketing department to close design specifications, define block/core/chip architectures, carry out and verify the design.
Need to Have:
  • Communications/DSP algorithm and efficient implementations.
  • System-on-the-chip architectures
  • Knowledge and hand-on experience from industry ASIC design flow including RTL coding, debugging/verification, synthesizing and supporting timing closure.
  • Design experience in Communications/DSP building blocks and/or SOC functional modules.
  • Experience with design tools such as NCSIM (and/or VCS), Cadence RC or Synopsys DC compiler,
  • Experience with multiple IC tape-out in industry.
  • Experience in chip bring up and performance measurement for IC and systems in laboratory to characterize and debug building blocks
  • MS in EE with 12 years of experience or Ph.D. in EE with 10 years of experience.

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