Principal ASIC Design Engineer Description: Expertise in at least 3 of the following: communication system design, RF radio design, digital ASIC design, applications platforms, and semiconductor ...
Principal ASIC Design Engineer Description: Expertise in at least 3 of the following: communication system design, RF radio design, digital ASIC design, applications platforms, and semiconductor ...
Principal ASIC Design Engineer Description: Expertise in at least 3 of the following: communication system design, RF radio design, digital ASIC design, applications platforms, and semiconductor ...
Principal ASIC Design Engineer Description: Expertise in at least 3 of the following: communication system design, RF radio design, digital ASIC design, applications platforms, and semiconductor ...
Principal ASIC Design Engineer (Starshield)
Hawthorne, CA · On-site
$200K - $285K/yr
PRINCIPAL ASIC DESIGN ENGINEER (STARSHIELD) Starshield leverages SpaceX's Starlink technology and launch capability to support national security efforts. While Starlink is designed for consumer and ...
Principal ASIC Design Engineer (Starshield)
Hawthorne, CA · On-site
$200K - $285K/yr
PRINCIPAL ASIC DESIGN ENGINEER (STARSHIELD) Starshield leverages SpaceX's Starlink technology and launch capability to support national security efforts. While Starlink is designed for consumer and ...
Principal ASIC Design Engineer (Starshield)
Hawthorne, CA · On-site
$200K - $285K/yr
PRINCIPAL ASIC DESIGN ENGINEER (STARSHIELD) Starshield leverages SpaceX's Starlink technology and launch capability to support national security efforts. While Starlink is designed for consumer and ...
Principal ASIC Design Engineer (Starshield)
Hawthorne, CA · On-site
$200K - $285K/yr
PRINCIPAL ASIC DESIGN ENGINEER (STARSHIELD) Starshield leverages SpaceX's Starlink technology and launch capability to support national security efforts. While Starlink is designed for consumer and ...
About the Role We're looking for an experienced Principal Engineer/Manager to lead a small, high ... Lead and mentor a small team of FPGA/ASIC design engineers, including resource planning, project ...
Quick apply
About the Role We're looking for an experienced Principal Engineer/Manager to lead a small, high ... Lead and mentor a small team of FPGA/ASIC design engineers, including resource planning, project ...
Principal ASIC Design Engineer
$190K - $225K/yr
About the Role We're looking for an experienced Principal Engineer/Manager to lead a small, high ... Lead and mentor a small team of FPGA/ASIC design engineers, including resource planning, project ...
Principal ASIC Design Engineer
$190K - $225K/yr
About the Role We're looking for an experienced Principal Engineer/Manager to lead a small, high ... Lead and mentor a small team of FPGA/ASIC design engineers, including resource planning, project ...
Principal ASIC Design Engineer
Irvine, CA · On-site
About the Role We're looking for an experienced Principal Engineer/Manager to lead a small, high ... Lead and mentor a small team of FPGA/ASIC design engineers, including resource planning, project ...
Principal ASIC Design Engineer
Irvine, CA · On-site
About the Role We're looking for an experienced Principal Engineer/Manager to lead a small, high ... Lead and mentor a small team of FPGA/ASIC design engineers, including resource planning, project ...
Principal ASIC Design Engineer This role has been designed as 'Hybrid' with an expectation that you will work on average 2 days per week from an HPE office. Who We Are: Hewlett Packard Enterprise is ...
Principal ASIC Design Engineer This role has been designed as 'Hybrid' with an expectation that you will work on average 2 days per week from an HPE office. Who We Are: Hewlett Packard Enterprise is ...
Principal ASIC Design Engineer This role has been designed as 'Hybrid' with an expectation that you will work on average 2 days per week from an HPE office. Who We Are: Hewlett Packard Enterprise is ...
Principal ASIC Design Engineer This role has been designed as 'Hybrid' with an expectation that you will work on average 2 days per week from an HPE office. Who We Are: Hewlett Packard Enterprise is ...
Principal ASIC Design Engineer This role has been designed as 'Hybrid' with an expectation that you will work on average 2 days per week from an HPE office. Who We Are: Hewlett Packard Enterprise is ...
Principal ASIC Design Engineer This role has been designed as 'Hybrid' with an expectation that you will work on average 2 days per week from an HPE office. Who We Are: Hewlett Packard Enterprise is ...
Principal ASIC Design Engineer This role has been designed as 'Hybrid' with an expectation that you will work on average 2 days per week from an HPE office. Who We Are: Hewlett Packard Enterprise is ...
Principal ASIC Design Engineer This role has been designed as 'Hybrid' with an expectation that you will work on average 2 days per week from an HPE office. Who We Are: Hewlett Packard Enterprise is ...
Principal ASIC Design Engineer - Terawave
San Diego, CA · On-site
$325 - $376.84/hr
## Principal ASIC Design Engineer - TerawaveApplylocations: San Diego, CA: Central Texas: Kent, WA: Bay Area, CAtime type: Full timeposted on: Posted Todayjob requisition id: R69346Application close ...
Principal ASIC Design Engineer - Terawave
San Diego, CA · On-site
$325 - $376.84/hr
## Principal ASIC Design Engineer - TerawaveApplylocations: San Diego, CA: Central Texas: Kent, WA: Bay Area, CAtime type: Full timeposted on: Posted Todayjob requisition id: R69346Application close ...
Principal ASIC Design Engineer (Silicon Engineering)
Palo Alto, CA · On-site
$220K - $355K/yr
PRINCIPAL ASIC DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet ...
New
Principal ASIC Design Engineer (Silicon Engineering)
Palo Alto, CA · On-site
$220K - $355K/yr
PRINCIPAL ASIC DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet ...
New
Principal ASIC Design Engineer - Terawave
San Diego, CA · On-site
$269K - $376K/yr
We are seeking ASIC/SOC Design engineers who are critical to ensuring our RFIC/ASIC designs culminate in thoroughly designed and validated cutting-edge integrated circuits that drive Blue Origin ...
Principal ASIC Design Engineer - Terawave
San Diego, CA · On-site
$269K - $376K/yr
We are seeking ASIC/SOC Design engineers who are critical to ensuring our RFIC/ASIC designs culminate in thoroughly designed and validated cutting-edge integrated circuits that drive Blue Origin ...
Principal ASIC Design Engineer (Silicon Engineering)
Palo Alto, CA · On-site
$220K - $355K/yr
PRINCIPAL ASIC DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet ...
Principal ASIC Design Engineer (Silicon Engineering)
Palo Alto, CA · On-site
$220K - $355K/yr
PRINCIPAL ASIC DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet ...
Principal ASIC Engineer
El Segundo, CA · On-site
Principal ASIC Engineer Company: The Boeing Company Boeing Space, Intelligence & Weapons Systems ... And we're applying the latest digital IC design processes with industry-best tools to enable ...
Principal ASIC Engineer
El Segundo, CA · On-site
Principal ASIC Engineer Company: The Boeing Company Boeing Space, Intelligence & Weapons Systems ... And we're applying the latest digital IC design processes with industry-best tools to enable ...
Principal ASIC Design Engineer - Terawave
Bodega Bay, CA · On-site
$269K - $376K/yr
This role requires a highly skilled Design and Verification Engineer with extensive experience in ... ASIC to/from FPGA flow Minimum Qualifications * BS, MS in Electrical Engineering or a related ...
Principal ASIC Design Engineer - Terawave
Bodega Bay, CA · On-site
$269K - $376K/yr
This role requires a highly skilled Design and Verification Engineer with extensive experience in ... ASIC to/from FPGA flow Minimum Qualifications * BS, MS in Electrical Engineering or a related ...
Principal ASIC Engineer
El Segundo, CA · On-site
Principal ASIC Engineer Company: The Boeing Company Boeing Space, Intelligence & Weapons Systems ... And we're applying the latest digital IC design processes with industry-best tools to enable ...
Principal ASIC Engineer
El Segundo, CA · On-site
Principal ASIC Engineer Company: The Boeing Company Boeing Space, Intelligence & Weapons Systems ... And we're applying the latest digital IC design processes with industry-best tools to enable ...
Principal ASIC Design Engineer - Terawave
San Diego, CA · On-site
$269K - $376K/yr
This role requires a highly skilled Design and Verification Engineer with extensive experience in ... ASIC to/from FPGA flow Minimum Qualifications * BS, MS in Electrical Engineering or a related ...
Principal ASIC Design Engineer - Terawave
San Diego, CA · On-site
$269K - $376K/yr
This role requires a highly skilled Design and Verification Engineer with extensive experience in ... ASIC to/from FPGA flow Minimum Qualifications * BS, MS in Electrical Engineering or a related ...
Principal ASIC Design Verification Engineer
Los Angeles, CA · On-site
$190K - $285K/yr
The Role We are seeking a Principal ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define ...
Quick apply
Principal ASIC Design Verification Engineer
Los Angeles, CA · On-site
$190K - $285K/yr
The Role We are seeking a Principal ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define ...
Principal Asic Design Engineer information
What is the difference between Principal Asic Design Engineer vs Senior Asic Design Engineer?
| Aspect | Principal Asic Design Engineer | Senior Asic Design Engineer |
|---|---|---|
| Qualifications | Bachelor's or Master's in Electrical Engineering or Computer Engineering; extensive ASIC design experience | Bachelor's or Master's in Electrical Engineering or Computer Engineering; significant ASIC design experience |
| Work Environment | Leads design projects, mentors teams, collaborates with cross-functional teams | Performs complex ASIC design tasks, supports project development, collaborates with engineers |
| Responsibilities | Architects ASIC solutions, oversees design quality, guides junior engineers | Designs ASIC components, reviews work, implements design improvements |
The main difference is that the Principal Asic Design Engineer typically leads projects and mentors teams, while the Senior Asic Design Engineer focuses on executing complex design tasks. Both roles require strong ASIC design skills and relevant experience, but the principal level involves more leadership and strategic responsibilities.

Full-time
Re-posted 15 days ago
Job description
Description:
Expertise in at least 3 of the following: communication system design, RF radio design, digital ASIC design, applications platforms, and semiconductor device modeling.
Requirements:
Principal Engineer will be responsible for design and development from multiple ASIC blocks to a complete Core/Chip in communications/digital signal processing (DSP) IC products. These include building blocks/Cores for communication functions. The responsibility includes working with system engineering or product marketing department to close design specifications, define block/core/chip architectures, carry out and verify the design.
Need to Have:
- Communications/DSP algorithm and efficient implementations.
- System-on-the-chip architectures
- Knowledge and hand-on experience from industry ASIC design flow including RTL coding, debugging/verification, synthesizing and supporting timing closure.
- Design experience in Communications/DSP building blocks and/or SOC functional modules.
- Experience with design tools such as NCSIM (and/or VCS), Cadence RC or Synopsys DC compiler,
- Experience with multiple IC tape-out in industry.
- Experience in chip bring up and performance measurement for IC and systems in laboratory to characterize and debug building blocks
- MS in EE with 12 years of experience or Ph.D. in EE with 10 years of experience.