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Physical Design Engineer Parttime Jobs in California

Google

Physical Design Lead, ASIC

Sunnyvale, CA · On-site

$159K - $164K/yr

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. * 10 years of experience in physical design, including ...

Saratech

Design Engineer

Mission Viejo, CA · On-site

$30 - $50/hr

Saratech is seeking a part-time Design Engineer. You will assist the Engineering Services/Design ... Physical demands: * Follow detailed complex directions, reason and problem solve. * The person will ...

Saratech, Inc.

Design Engineer

Mission Viejo, CA

$30 - $50/hr

Saratech is seeking a part-time Design Engineer. You will assist the Engineering Services/Design ... Physical demands: * Follow detailed complex directions, reason and problem solve. * The person will ...

Interwest Group

Senior Civil Engineer Part Time

Pomona, CA · On-site

$40 - $50/hr

Senior Civil Engineer - Pomona, CA - Part Time Interwest Consulting Group was founded in 2002 and ... Any combination of civil design and/or civil plan check experience * Proficiency with Microsoft ...

Arcadis

Senior Process Design Engineer

Los Angeles, CA · On-site

$112K - $144K/yr

Arcadis is the world's leading company delivering sustainable design, engineering, and consultancy ... Arcadis offers benefits for full time and part time positions. These benefits include medical ...

Efficient Computer

Lead STA Engineer

San Jose, CA · On-site

$200K - $250K/yr

Knowledge of physical design and ASIC implementation * Experience in full chip sign-off budgeting ... PD engineers. * Definition of design constraints for static timing analysis (synthesis, pre/post ...

Leidos

RCDD Telecom Design Engineer

San Diego, CA

$116K - $210K/yr

The Leidos Technology and Digital Transformation Solutions Division is looking to add a part-time ... design for building and campuses. * Engineering degree desired but not required * Must be a US ...

Leidos

RCDD Telecom Design Engineer

San Diego, CA · On-site

$116K - $210K/yr

The Leidos Technology and Digital Transformation Solutions Division is looking to add a part-time ... design for building and campuses. * Engineering degree desired but not required * Must be a US ...

Leidos

RCDD Telecom Design Engineer

Chula Vista, CA · On-site

$116K - $210K/yr

... add a part-time team member to our San Diego based utility telecom and networking team who can ... origin, citizenship, religion, physical or mental disability, medical condition, genetic ...

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Physical Design Engineer Parttime information

What is the difference between Physical Design Engineer Parttime vs Physical Design Engineer?

AspectPhysical Design Engineer ParttimePhysical Design Engineer
Work HoursPart-time, fewer hours per weekFull-time, standard hours
ResponsibilitiesAssists in physical design tasks, limited scopeLeads entire physical design process from synthesis to tape-out
CredentialsBachelor's or Master's in EDA, VLSI designSimilar credentials, often with more experience
Work EnvironmentTypically remote or flexibleOn-site or hybrid in design teams

Physical Design Engineer Parttime roles focus on supporting specific tasks with flexible hours, while full-time Physical Design Engineers handle comprehensive design responsibilities. Both roles require similar educational backgrounds and skills, but differ mainly in work hours and scope of responsibilities.

What are popular job titles related to Physical Design Engineer Parttime jobs in California? For Physical Design Engineer Parttime jobs in California, the most frequently searched job titles are:
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Physical Design Engineer Parttime jobs near you
Physical Design Lead, ASIC

Physical Design Lead, ASIC

Google

Sunnyvale, CA • On-site

$159K - $164K/yr

Part-time

Posted 12 days ago

Google rating

8.8

Company rating: 8.8 out of 10

Based on 101 frontline employees who took The Breakroom Quiz

40th of 209 rated software companies

Job description

Minimum qualifications:
  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  • 10 years of experience in physical design, including custom structured datapath implementation.
  • Experience hardening dense compute units (such as dot-product engines, multiplier-accumulator (MACs), multipliers, or arithmetic logic unit (ALUs) into high-frequency, low-power macros.
  • Experience in sub-7nm process nodes (including FinFET and Gate-All-Around architectures), managing the physical density and routing congestion typical of custom datapaths.

Preferred qualifications:
  • Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with focus on computer architecture.
  • Experience in structured placement methodologies (e.g., relative placement, data-flow driven layout, and customized power-grid stitching for dense blocks).
  • Experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality; familiarity with tools for schematics, layout, and circuit/logic simulation.
  • Experience with physical design and timing, with managing PT-to-PnR timing correlations and metal-fill impacts on dense structures.
  • Expert-level scripting versatility (Tcl, Python, Perl) to build layout automation and structural constraints within standard EDA tools.

About the job
In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
In this role, you will be empowering Google and our customers with breakthrough capabilities by delivering transformational, co-optimized silicon and technology leadership at scale.
The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $192000 - $279000 (USD) 20% bonus target equity benefits
Learn more about benefits at Google .
Responsibilities
  • Own critical custom datapath and matrix multiplication accumulator blocks, driving execution from RTL-to-GDSII including synthesis, floor-planning, place and route (PNR), timing closure, and physical signoff.
  • Understand math-intensive micro-architecture to perform detailed feasibility studies, analyzing performance, power, and area (PPA) tradeoffs to achieve optimal design closure.
  • Develop and improve advanced physical design methodologies and customize implementation recipes, specifically optimizing PPA across complex arithmetic pipeline structures. Manage different PNR tools - synopsys fusion compiler, cadence (Innovus/Genus), PrimeTime, StarRC, Calibre, Apache Redhawk.
  • Implement and execute key design phases: floor-planning, synthesis, placement, clock tree synthesis (CTS), timing closure, routing, extraction, physical verification (design rule checking (DRC)/layout versus schematic (LVS), electromigration (EM)/IR, and final signoff.
  • Lead sub-chip execution and drive delivery, providing direct technical guidance and mentorship to a small team of engineers to ensure on-schedule project completion.

Information collected and processed as part of your Google Careers profile, and any job applications you choose to submit is subject to Google's Applicant and Candidate Privacy Policy .
Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire .
If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form .
Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.
To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees, or any other organization location. Google is not responsible for any fees related to unsolicited resumes.
Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.

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