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Soc Physical Design Engineer Jobs in California (NOW HIRING)

Search Tactics LLC

Physical Design Engineer

San Jose, CA · On-site

$159K - $164K/yr

Physical Design Engineer Location: San Jose, CA Hybrid Duration: 12 Months VISA: H-1, USC Position ... Key Responsibilities Execute RTL synthesis for complex ASIC and SoC designs using Cadence Genus.

search-tactics

Physical Design Engineer

San Jose, CA · On-site

$70 - $80/hr

Physical Design Engineer Location: San Jose, CA Hybrid Duration: 12 Months VISA: H-1, GC, USC is ... Key Responsibilities Execute RTL synthesis for complex ASIC and SoC designs using Cadence Genus.

Micron

HBM SoC Physical Design Engineer

Folsom, CA

$121K - $205K/yr

As a SoC Physical Design Engineer in the Heterogeneous Integration Group (HIG), you will drive the implementation of advanced HBM SoC logic/base die designs from netlist to GDSII. You will work ...

Apple

SoC Physical Design Engineer, PnR

San Jose, CA · On-site

$159K - $164K/yr

Experience with physical design construction and analysis flows and methodology. Preferred Qualifications MS in Electrical/Electronics/Computer Engineering or related field. Experience with large SOC ...

Apple

SoC Physical Design Engineer, PnR

San Jose, CA · On-site

$159K - $164K/yr

... physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC ... Preferred Qualifications MS in Electrical/Electronics/Computer Engineering or related field.

Apple

SoC Physical Design Engineer, PnR

San Diego, CA · On-site

$144K - $148K/yr

... physical design construction and analysis flows and methodology Preferred Qualifications MS in Electrical/Electronics/Computer Engineering or related field Experience with large SOC designs (>20M ...

Apple

SoC Physical Design Engineer, PnR

San Jose, CA

$184K - $324K/yr

... physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC ... Preferred Qualifications MS in Electrical/Electronics/Computer Engineering or related field.

Apple

SoC Physical Design Engineer, PnR

San Diego, CA

$175K - $308K/yr

... physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC ... Preferred Qualifications MS in Electrical/Electronics/Computer Engineering or related field ...

Apple

SoC Physical Design Engineer, PnR

San Jose, CA

$184K - $324K/yr

... physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC ... Preferred Qualifications MS in Electrical/Electronics/Computer Engineering or related field.

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Soc Physical Design Engineer information

See California salary details

$93.8K

$139.6K

How much do soc physical design engineer jobs pay per year?

As of Aug 14, 2026, the average yearly pay for soc physical design engineer in California is $137,583.00, according to ZipRecruiter salary data. Most workers in this role earn between $134,200.00 and $138,200.00 per year, depending on experience, location, and employer.

What is a SoC Physical Design Engineer?

SoC Physical Design Engineers are professionals who specialize in the layout and implementation of System-on-Chip (SoC) designs at the physical level. They are responsible for translating logical circuit designs into physical layouts that can be manufactured on silicon chips. Their tasks include floorplanning, placement, routing, timing analysis, and ensuring design for manufacturability. These engineers work closely with other teams to optimize power, performance, and area (PPA) while meeting strict technical specifications.

What skills and qualifications are needed to be a SoC Physical Design Engineer?

To thrive as a SoC Physical Design Engineer, you need a solid background in electrical engineering, digital logic design, and ASIC/FPGA development, usually supported by a relevant degree. Proficiency with EDA tools such as Cadence, Synopsys, and Mentor Graphics, as well as understanding of scripting languages like TCL and Perl, is typically required. Attention to detail, problem-solving skills, and effective teamwork are crucial soft skills for excelling in this role. These competencies ensure precise, efficient chip layouts that meet performance, power, and area targets in complex semiconductor projects.

What challenges do SoC Physical Design Engineers face during the tape-out phase, and how can they be addressed?

SoC Physical Design Engineers often encounter challenges such as meeting tight timing closure, managing power consumption, and resolving congestion during the tape-out phase. These issues require close collaboration with verification, synthesis, and DFT teams to iteratively optimize the physical layout and ensure all design constraints are satisfied. Effective use of EDA tools, proactive communication, and attention to detail are essential to address last-minute design rule violations and to deliver a high-quality, manufacturable chip on schedule.

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Infographic showing various Soc Physical Design Engineer job openings in California as of August 2026, with employment types broken down into 100% Full Time. Highlights an 100% In-person job distribution, with an average salary of $137,583 per year, or $66.1 per hour.

HBM SoC Physical Design Engineer

Micron Technology, Inc

Folsom, CA • On-site

$121 - $205/hr

Other

Medical, Dental, Vision, PTO

Re-posted 7 days ago

Micron Technology rating

8.6

Company rating: 8.6 out of 10

Based on 43 frontline employees who took The Breakroom Quiz

27th of 157 rated electronics manufacturers

Job description

Req ID: JR107315 HBM SoC Physical Design Engineer

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

As a SoC Physical Design Engineer in the Heterogenous Integration Group (HIG), you will drive the implementation of advanced HBM SoC logic/base die designs from netlist to GDSII. You will work closely with RTL design, verification, DFT, IP providers, packaging/assembly, and manufacturing teams to deliver best-in-class PPA (performance, power, area) and robust signoff collateral for tape-out. This is a hands-on role with opportunities to own blocks or top-level integration across multiple product generations. You will also work on efforts to enable and integrate AI-driven tools and AI-enabled workflows into the team's methodologies.

Key Responsibilities
  • Own physical implementation for SoC blocks and/or top-level, including floor-planning, placement, CTS, routing, and physical optimization to meet PPA targets.
  • Drive timing closure (setup/hold) across multi-mode/multi-corner (MMMC) scenarios; partner with RTL, architecture, and STA/signoff to converge designs.
  • Integrate and implement complex IP (e.g., controllers, microcontrollers, NOC, interfaces, MBIST/DFT logic, buffers, PHY-adjacent logic) with focus on robust physical integration and timing/power integrity.
  • Perform and/or coordinate physical signoff, including DRC/LVS, IR drop/EM, and timing signoff, addressing violations efficiently.
  • Partner with DFT teams to ensure scan/MBIST requirements are physically realizable and do not compromise PPA or schedule.
  • Work with packaging, assembly, test, probe, and manufacturing collaborators to ensure builds meet manufacturability and quality requirements.
  • Support tape-out execution (checklists, ECO flows, signoff reviews) and contribute to post-silicon debug by correlating silicon behavior with PD/STA/power analysis.
  • Identify flow gaps and improve productivity through scripting/automation and best-practice methodology development.
Required Qualifications
  • Strong experience in SoC physical design implementation from netlist to GDSII on advanced nodes and complex designs.
  • Proficiency with industry EDA tools (e.g., Cadence Innovus/Tempus, Synopsys ICC2/PrimeTime, Siemens Calibre or equivalent).
  • Solid understanding of STA fundamentals, clocking, constraints (SDC), and common closure techniques (buffering, path shaping, useful skew, etc.).
  • Experience with power intent and power delivery considerations (e.g., UPF/CPF concepts, power grid planning, power gating implications).
  • Familiarity with physical verification/signoff concepts: DRC, LVS, ERC, parasitic extraction awareness, and signoff handoff quality.
Preferred Qualifications
  • Experience with HBM / DRAM adjacent SoC designs, or memory-subsystem-heavy SoCs.
  • Bachelor's or master's degree in electrical engineering, Computer Engineering, or a related field.
  • Minimum 3 years of experience in a related field.
  • Proven ability to mentor and develop engineers early in their careers.
  • Good understanding of Agentic AI or willingness to learn Agentic AI to help develop efficient workflow.
Job Profile(s):

Systems Design Engineer 3

Relocation Level: TBD

The US base salary range that Micron Technology estimates it could pay for this full-time position is:

$121,000.00 - $205,000.00 a year

Additional compensation may include benefits, bonuses and equity. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target base pay for new hire salaries of the position across all US locations. Within the range, individual pay is determined by work location and additional job-related factors, including knowledge, skills, experience, tenure and relevant education or training. The pay scale is subject to change depending on business needs. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits.

As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on Benefits | Micron Technology, Inc

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.

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