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Soc Physical Design Engineer Jobs (NOW HIRING)

Search Tactics LLC

Physical Design Engineer

San Jose, CA · On-site

$159K - $164K/yr

Physical Design Engineer Location: San Jose, CA Hybrid Duration: 12 Months VISA: H-1, USC Position ... Key Responsibilities Execute RTL synthesis for complex ASIC and SoC designs using Cadence Genus.

New

search-tactics

Physical Design Engineer

San Jose, CA · On-site

$70 - $80/hr

Physical Design Engineer Location: San Jose, CA Hybrid Duration: 12 Months VISA: H-1, GC, USC is ... Key Responsibilities Execute RTL synthesis for complex ASIC and SoC designs using Cadence Genus.

New

Micron

HBM SoC Physical Design Engineer

Richardson, TX

$123K - $127K/yr

As a SoC Physical Design Engineer in the Heterogeneous Integration Group (HIG), you will drive the implementation of advanced HBM SoC logic/base die designs from netlist to GDSII. You will work ...

Micron

HBM SoC Physical Design Engineer

Richardson, TX · On-site

$123K - $127K/yr

As a SoC Physical Design Engineer in the Heterogeneous Integration Group (HIG), you will drive the implementation of advanced HBM SoC logic/base die designs from netlist to GDSII. You will work ...

Apple

SoC Physical Design Engineer, PnR

Beaverton, OR

$141K - $145K/yr

... physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC ... Preferred Qualifications MS in Electrical/Electronics/Computer Engineering or related field.

Apple

SoC Physical Design Engineer, PnR

Beaverton, OR · On-site

$141K - $145K/yr

... physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC ... Engineering or related field. Experience with partition level P&R implementation including ...

Apple

SoC Physical Design Engineer, PnR

Beaverton, OR

$141K - $145K/yr

... physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC ... Preferred Qualifications MS in Electrical/Electronics/Computer Engineering or related field.

Apple

SoC Physical Design Engineer, PnR

San Jose, CA · On-site

$159K - $164K/yr

Experience with physical design construction and analysis flows and methodology. Preferred Qualifications MS in Electrical/Electronics/Computer Engineering or related field. Experience with large SOC ...

Apple

SoC Physical Design Engineer, PnR

San Jose, CA · On-site

$159K - $164K/yr

... physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC ... Preferred Qualifications MS in Electrical/Electronics/Computer Engineering or related field.

Apple

SoC Physical Design Engineer, PnR

San Diego, CA · On-site

$144K - $148K/yr

... physical design construction and analysis flows and methodology Preferred Qualifications MS in Electrical/Electronics/Computer Engineering or related field Experience with large SOC designs (>20M ...

Apple

SoC Physical Design Engineer, PnR

Beaverton, OR · On-site

$141K - $145K/yr

... physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC ... Preferred Qualifications MS in Electrical/Electronics/Computer Engineering or related field.

Apple

SoC Physical Design Engineer, PnR

Beaverton, OR · On-site

$141K - $145K/yr

... physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC ... Preferred Qualifications MS in Electrical/Electronics/Computer Engineering or related field.

Apple

SoC Physical Design Engineer, PnR

San Jose, CA

$184K - $324K/yr

... physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC ... Preferred Qualifications MS in Electrical/Electronics/Computer Engineering or related field.

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Soc Physical Design Engineer information

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$95K

$141.5K

How much do soc physical design engineer jobs pay per year?

As of Aug 1, 2026, the average yearly pay for soc physical design engineer in the United States is $139,408.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $140,000.00 per year, depending on experience, location, and employer.

What are SoC Physical Design Engineers?

SoC Physical Design Engineers are professionals who specialize in the layout and implementation of System-on-Chip (SoC) designs at the physical level. They are responsible for translating logical circuit designs into physical layouts that can be manufactured on silicon chips. Their tasks include floorplanning, placement, routing, timing analysis, and ensuring design for manufacturability. These engineers work closely with other teams to optimize power, performance, and area (PPA) while meeting strict technical specifications.

What are the key skills and qualifications needed to thrive as a SoC Physical Design Engineer, and why are they important?

To thrive as a SoC Physical Design Engineer, you need a solid background in electrical engineering, digital logic design, and ASIC/FPGA development, usually supported by a relevant degree. Proficiency with EDA tools such as Cadence, Synopsys, and Mentor Graphics, as well as understanding of scripting languages like TCL and Perl, is typically required. Attention to detail, problem-solving skills, and effective teamwork are crucial soft skills for excelling in this role. These competencies ensure precise, efficient chip layouts that meet performance, power, and area targets in complex semiconductor projects.

What are some common challenges faced by SoC Physical Design Engineers during the tape-out phase, and how can they be addressed?

SoC Physical Design Engineers often encounter challenges such as meeting tight timing closure, managing power consumption, and resolving congestion during the tape-out phase. These issues require close collaboration with verification, synthesis, and DFT teams to iteratively optimize the physical layout and ensure all design constraints are satisfied. Effective use of EDA tools, proactive communication, and attention to detail are essential to address last-minute design rule violations and to deliver a high-quality, manufacturable chip on schedule.
More about Soc Physical Design Engineer jobs
What cities are hiring for Soc Physical Design Engineer jobs? Cities with the most Soc Physical Design Engineer job openings:
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Soc Physical Design Engineer jobs near you
Infographic showing various Soc Physical Design Engineer job openings in the United States as of July 2026, with employment types broken down into 88% Full Time, 9% Part Time, and 3% Contract. Highlights an 85% Physical, 4% Hybrid, and 11% Remote job distribution, with an average salary of $139,408 per year, or $67 per hour.

Physical Design Engineer

Search Tactics LLC

San Jose, CA • On-site

$159K - $164K/yr

Other

Posted 3 days ago

New

Job description

Position: Physical Design Engineer
Location: San Jose, CA Hybrid

Duration: 12 Months

VISA: H-1, USC

Position Overview

We are seeking an experienced Physical Design Engineer to support the implementation of high-performance semiconductor designs targeting advanced process technologies. This contract position will focus on synthesis, floorplanning, physical implementation, and performance optimization for complex, timing-sensitive designs while working closely with cross-functional engineering teams.

Key Responsibilities

Execute RTL synthesis for complex ASIC and SoC designs using Cadence Genus.

Optimize designs for power, performance, and area (PPA) throughout the synthesis and physical design flow.

Develop and improve floorplans using Cadence Innovus, ensuring efficient utilization and routing.

Collaborate with RTL, architecture, and design teams to provide feedback on timing, constraints, and implementation strategies.

Partner with physical implementation and place-and-route teams to achieve timing closure and design quality goals.

Analyze timing challenges, identify critical paths, and recommend design improvements to improve convergence.

Support physical implementation activities from synthesis through implementation while maintaining design quality and schedule objectives.

Required Qualifications

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related discipline.

5+ years of experience in ASIC or SoC Physical Design.

Hands-on expertise with Cadence Genus for synthesis and Cadence Innovus for floorplanning and implementation.

Experience working on large, high-performance semiconductor designs with demanding timing requirements.

Strong knowledge of synthesis, timing analysis, physical implementation, and PPA optimization.

Experience with advanced semiconductor process technologies such as 5nm, 3nm, or newer.

Excellent communication skills and the ability to work effectively with RTL, architecture, physical design, and implementation teams.

Preferred Qualifications

Experience supporting complex SoC, AI, HPC, or accelerator designs.

Strong understanding of timing closure methodologies and synthesis-to-implementation correlation.

Familiarity with advanced implementation flows, design constraints, and physical optimization techniques.

Proven ability to collaborate with globally distributed engineering teams to deliver successful silicon implementations.

Apply