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Soc Physical Design Engineer Jobs (NOW HIRING)

Micron

HBM SoC Physical Design Engineer

Richardson, TX

$146K - $309K/yr

As a SoC Physical Design Engineer in the Heterogeneous Integration Group (HIG), you will drive the implementation of advanced HBM SoC logic/base die designs from netlist to GDSII. You will work ...

Micron

HBM SoC Physical Design Engineer

Richardson, TX

$123.50K - $127.10K/yr

As a SoC Physical Design Engineer in the Heterogeneous Integration Group (HIG), you will drive the implementation of advanced HBM SoC logic/base die designs from netlist to GDSII. You will work ...

Micron

HBM SoC Physical Design Engineer

Folsom, CA

$146K - $309K/yr

As a SoC Physical Design Engineer in the Heterogeneous Integration Group (HIG), you will drive the implementation of advanced HBM SoC logic/base die designs from netlist to GDSII. You will work ...

Apple

SoC Physical Design Engineer, PnR

Beaverton, OR · On-site

$141.50K - $145.70K/yr

... physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC ... Preferred Qualifications MS in Electrical/Electronics/Computer Engineering or related field.

Apple

SoC Physical Design Engineer, PnR

Beaverton, OR · On-site

$141.50K - $145.70K/yr

... physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC ... Minimum BS and 0+ years of industry experience MS in Electrical/Electronics/Computer Engineering or ...

Apple

SoC Physical Design Engineer, PnR

Beaverton, OR · On-site

$141.50K - $145.70K/yr

... physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC ... Preferred Qualifications MS in Electrical/Electronics/Computer Engineering or related field.

Apple

SoC Physical Design Engineer, PnR

San Jose, CA · On-site

$159.40K - $164.10K/yr

... physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC ... MS in Electrical/Electronics/Computer Engineering or related field.Experience with large SOC ...

Apple

SoC Physical Design Engineer, PnR

San Jose, CA · On-site

$159.40K - $164.10K/yr

Experience with physical design construction and analysis flows and methodology. MS in Electrical/Electronics/Computer Engineering or related field.Experience with large SOC designs (>20M gates) with ...

Apple

SoC Physical Design Engineer, PnR

Beaverton, OR · On-site

$141.50K - $145.70K/yr

... physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC ... Minimum BS and 0+ years of industry experience MS in Electrical/Electronics/Computer Engineering or ...

Apple

SoC Physical Design Engineer, PnR

Beaverton, OR · On-site

$141.50K - $145.70K/yr

... physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC ... MS in Electrical/Electronics/Computer Engineering or related field.Experience with partition level ...

Apple

SoC Physical Design Engineer, PnR

Beaverton, OR

$141.50K - $145.70K/yr

... physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC ... Preferred Qualifications MS in Electrical/Electronics/Computer Engineering or related field.

Apple

SoC Physical Design Engineer, PnR

San Jose, CA

$181.10K - $318.40K/yr

... physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC ... Preferred Qualifications MS in Electrical/Electronics/Computer Engineering or related field.

Apple

SoC Physical Design Engineer, PnR

San Jose, CA

$181.10K - $318.40K/yr

... physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC ... Preferred Qualifications MS in Electrical/Electronics/Computer Engineering or related field.

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How much do soc physical design engineer jobs pay per year?

As of May 31, 2026, the average yearly pay for soc physical design engineer in the United States is $139,408.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $140,000.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a SoC Physical Design Engineer, and why are they important?

To thrive as a SoC Physical Design Engineer, you need a solid background in electrical engineering, digital logic design, and ASIC/FPGA development, usually supported by a relevant degree. Proficiency with EDA tools such as Cadence, Synopsys, and Mentor Graphics, as well as understanding of scripting languages like TCL and Perl, is typically required. Attention to detail, problem-solving skills, and effective teamwork are crucial soft skills for excelling in this role. These competencies ensure precise, efficient chip layouts that meet performance, power, and area targets in complex semiconductor projects.

What are some common challenges faced by SoC Physical Design Engineers during the tape-out phase, and how can they be addressed?

SoC Physical Design Engineers often encounter challenges such as meeting tight timing closure, managing power consumption, and resolving congestion during the tape-out phase. These issues require close collaboration with verification, synthesis, and DFT teams to iteratively optimize the physical layout and ensure all design constraints are satisfied. Effective use of EDA tools, proactive communication, and attention to detail are essential to address last-minute design rule violations and to deliver a high-quality, manufacturable chip on schedule.

What are SoC Physical Design Engineers?

SoC Physical Design Engineers are professionals who specialize in the layout and implementation of System-on-Chip (SoC) designs at the physical level. They are responsible for translating logical circuit designs into physical layouts that can be manufactured on silicon chips. Their tasks include floorplanning, placement, routing, timing analysis, and ensuring design for manufacturability. These engineers work closely with other teams to optimize power, performance, and area (PPA) while meeting strict technical specifications.
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Soc Physical Design Engineer jobs near you

SoC Top-Level Physical Design Engineer

Tenstorrent

Austin, TX • On-site

$100K - $500K/yr

Full-time

Posted 9 days ago

Job description

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.
Tenstorrent is seeking an exceptional Senior-level SoC Physical Design Engineer to drive top-level implementation of our complex AI and CPU SoC designs. You'll orchestrate cross-disciplinary collaboration, implementing sophisticated floorplans, power grids, and clock networks while ensuring design closure at the chip level. If you excel at managing the complexity of full-chip physical design and want to deliver next-generation AI hardware, we need your expertise.
This role ishybrid, based out of Santa Clara, CA; Austin, TX; or Ft. Collins, CO.
We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.
Who You Are
  • A seasoned physical design engineer who thrives on complex, full-chip implementation challenges.
  • Expert at collaborating across disciplines, working effectively with architecture, RTL, and packaging teams.
  • Passionate about optimizing chip-level implementations for power, performance, and area.
  • Detail-oriented professional who drives design closure while maintaining quality and meeting aggressive schedules

What We Need
  • 8+ years of top-level SOC physical design experience on complex, multi-million gate designs.
  • Deep expertise in hierarchical floorplanning, fabric implementation, power grid design, and global clock distribution.
  • Proven track record with bump planning, RDL implementation, and multi-voltage domain designs.
  • Mastery of timing closure, EM/IR analysis, and physical verification at the chip level.

What You Will Learn
  • How to implement cutting-edge AI accelerators and high-performance CPUs at the SOC level.
  • Advanced techniques for chiplet integration and next-generation packaging co-design.
  • Strategies for optimizing massive designs with complex power domains and clock architectures.
  • Methods for driving successful chip-level closure through effective cross-functional collaboration.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.
Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.
This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.

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