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Soc Physical Design Engineer Jobs (NOW HIRING)

Micron

HBM SoC Physical Design Engineer

Richardson, TX

$146K - $309K/yr

As a SoC Physical Design Engineer in the Heterogeneous Integration Group (HIG), you will drive the implementation of advanced HBM SoC logic/base die designs from netlist to GDSII. You will work ...

Micron

HBM SoC Physical Design Engineer

Richardson, TX

$123K - $127K/yr

As a SoC Physical Design Engineer in the Heterogeneous Integration Group (HIG), you will drive the implementation of advanced HBM SoC logic/base die designs from netlist to GDSII. You will work ...

Micron

HBM SoC Physical Design Engineer

Richardson, TX

$123K - $127K/yr

As a SoC Physical Design Engineer in the Heterogeneous Integration Group (HIG), you will drive the implementation of advanced HBM SoC logic/base die designs from netlist to GDSII. You will work ...

Micron

HBM SoC Physical Design Engineer

Folsom, CA

$146K - $309K/yr

As a SoC Physical Design Engineer in the Heterogeneous Integration Group (HIG), you will drive the implementation of advanced HBM SoC logic/base die designs from netlist to GDSII. You will work ...

Apple

SoC Physical Design Engineer, PnR

Beaverton, OR · On-site

$141K - $145K/yr

... physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC ... Minimum BS and 0+ years of industry experience MS in Electrical/Electronics/Computer Engineering or ...

Apple

SoC Physical Design Engineer, PnR

Beaverton, OR · On-site

$141K - $145K/yr

... physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC ... Preferred Qualifications MS in Electrical/Electronics/Computer Engineering or related field.

Apple

SoC Physical Design Engineer, PnR

San Jose, CA · On-site

$159K - $164K/yr

... physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC ... MS in Electrical/Electronics/Computer Engineering or related field.Experience with large SOC ...

Apple

SoC Physical Design Engineer, PnR

San Jose, CA · On-site

$159K - $164K/yr

Experience with physical design construction and analysis flows and methodology. MS in Electrical/Electronics/Computer Engineering or related field.Experience with large SOC designs (>20M gates) with ...

Apple

SoC Physical Design Engineer, PnR

Beaverton, OR · On-site

$141K - $145K/yr

... physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC ... Preferred Qualifications MS in Electrical/Electronics/Computer Engineering or related field.

Apple

SoC Physical Design Engineer, PnR

Beaverton, OR · On-site

$141K - $145K/yr

... physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC ... Minimum BS and 0+ years of industry experience MS in Electrical/Electronics/Computer Engineering or ...

Apple

SoC Physical Design Engineer, PnR

Beaverton, OR · On-site

$141K - $145K/yr

... physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC ... MS in Electrical/Electronics/Computer Engineering or related field.Experience with partition level ...

Apple

SoC Physical Design Engineer, PnR

Beaverton, OR

$141K - $145K/yr

... physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC ... Preferred Qualifications MS in Electrical/Electronics/Computer Engineering or related field.

Apple

SoC Physical Design Engineer, PnR

San Jose, CA

$181K - $318K/yr

... physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC ... Preferred Qualifications MS in Electrical/Electronics/Computer Engineering or related field.

Apple

SoC Physical Design Engineer, PnR

San Jose, CA

$181K - $318K/yr

... physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC ... Preferred Qualifications MS in Electrical/Electronics/Computer Engineering or related field.

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Soc Physical Design Engineer information

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$95K

$141.5K

How much do soc physical design engineer jobs pay per year?

As of Jun 20, 2026, the average yearly pay for soc physical design engineer in the United States is $139,408.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $140,000.00 per year, depending on experience, location, and employer.

What are SoC Physical Design Engineers?

SoC Physical Design Engineers are professionals who specialize in the layout and implementation of System-on-Chip (SoC) designs at the physical level. They are responsible for translating logical circuit designs into physical layouts that can be manufactured on silicon chips. Their tasks include floorplanning, placement, routing, timing analysis, and ensuring design for manufacturability. These engineers work closely with other teams to optimize power, performance, and area (PPA) while meeting strict technical specifications.

What does SOC stand for?

In the context of a SoC Physical Design Engineer, SOC stands for System on Chip, which refers to an integrated circuit that consolidates multiple electronic components such as processors, memory, and peripherals onto a single chip. This role involves designing and optimizing the physical layout of these complex chips using tools like CAD and EDA software.

What are the key skills and qualifications needed to thrive as a SoC Physical Design Engineer, and why are they important?

To thrive as a SoC Physical Design Engineer, you need a solid background in electrical engineering, digital logic design, and ASIC/FPGA development, usually supported by a relevant degree. Proficiency with EDA tools such as Cadence, Synopsys, and Mentor Graphics, as well as understanding of scripting languages like TCL and Perl, is typically required. Attention to detail, problem-solving skills, and effective teamwork are crucial soft skills for excelling in this role. These competencies ensure precise, efficient chip layouts that meet performance, power, and area targets in complex semiconductor projects.

What is SOC in technology?

In the context of a SOC Physical Design Engineer, SOC stands for System on Chip, which is an integrated circuit that consolidates multiple electronic components such as processors, memory, and peripherals onto a single chip. Designing SOCs involves hardware description languages, verification tools, and understanding of digital circuit design to optimize performance and power consumption.

What are some common challenges faced by SoC Physical Design Engineers during the tape-out phase, and how can they be addressed?

SoC Physical Design Engineers often encounter challenges such as meeting tight timing closure, managing power consumption, and resolving congestion during the tape-out phase. These issues require close collaboration with verification, synthesis, and DFT teams to iteratively optimize the physical layout and ensure all design constraints are satisfied. Effective use of EDA tools, proactive communication, and attention to detail are essential to address last-minute design rule violations and to deliver a high-quality, manufacturable chip on schedule.

What is a SOC in slang?

In the context of a SOC Physical Design Engineer, SOC in slang often refers to a 'System on Chip,' which is an integrated circuit that consolidates multiple components such as processors, memory, and peripherals onto a single chip. Understanding SOCs is essential for designing efficient hardware and optimizing chip performance using tools like EDA software. Knowledge of digital design and verification is also important in this role.

What is SOC in EV charging?

In the context of a SOC Physical Design Engineer, SOC in EV charging refers to the State of Charge, which indicates the current battery level of an electric vehicle. Designing SOC management systems involves integrating hardware and software to accurately monitor and control battery charging and discharging processes, ensuring safety and efficiency. Knowledge of power electronics, battery management systems, and embedded design tools is essential for this role.
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Infographic showing various Soc Physical Design Engineer job openings in the United States as of June 2026, with employment types broken down into 3% Full Time, 96% Part Time, and 1% Temporary. Highlights an 81% Physical, 6% Hybrid, and 13% Remote job distribution, with an average salary of $139,408 per year, or $67 per hour.
HBM SoC Physical Design Engineer

HBM SoC Physical Design Engineer

Micron Technology

Richardson, TX • On-site

$123K - $127K/yr

Full-time

Medical, Dental, Vision, PTO

Posted 27 days ago

Micron Technology rating

8.7

Company rating: 8.7 out of 10

Based on 39 frontline employees who took The Breakroom Quiz

11th of 139 rated electronics manufacturers

Job description

Our vision is to transform how the world uses information to enrich life for all.
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
As a SoC Physical Design Engineer in the Heterogeneous Integration Group (HIG), you will drive the implementation of advanced HBM SoC logic/base die designs from netlist to GDSII. You will work closely with RTL design, verification, DFT, IP providers, packaging/assembly, and manufacturing teams to deliver best-in-class PPA (performance, power, area) and robust signoff collateral for tape-out. This is a hands-on role with opportunities to own blocks or top-level integration across multiple product generations.
Key Responsibilities
  • Own physical implementation for SoC blocks and/or top-level, including floor-planning, placement, CTS, routing, and physical optimization to meet PPA targets.
  • Drive timing closure (setup/hold) across multi-mode/multi-corner (MMMC) scenarios; partner with RTL, architecture, and STA/signoff to converge designs.
  • Integrate and implement complex IP (e.g., controllers, microcontrollers, NOC, interfaces, MBIST/DFT logic, buffers, PHY-adjacent logic) with focus on robust physical integration and timing/power integrity.
  • Perform and/or coordinate physical signoff, including DRC/LVS, IR drop/EM, and timing signoff, addressing violations efficiently.
  • Partner with DFT teams to ensure scan/MBIST requirements are physically realizable and do not compromise PPA or schedule.
  • Work with packaging, assembly, test, probe, and manufacturing collaborators to ensure builds meet manufacturability and quality requirements.
  • Support tape-out execution (checklists, ECO flows, signoff reviews) and contribute to post-silicon debug by correlating silicon behavior with PD/STA/power analysis.
  • Identify flow gaps and improve productivity through scripting/automation and best-practice methodology development.

Required Qualifications
  • Strong experience in SoC physical design implementation from netlist to GDSII on advanced nodes and complex designs.
  • Proficiency with industry EDA tools (e.g., Cadence Innovus/Tempus, Synopsys ICC2/PrimeTime, Siemens Calibre or equivalent).
  • Solid understanding of STA fundamentals, clocking, constraints (SDC), and common closure techniques (buffering, path shaping, useful skew, etc.).
  • Experience with power intent and power delivery considerations (e.g., UPF/CPF concepts, power grid planning, power gating implications).
  • Familiarity with physical verification/signoff concepts: DRC, LVS, ERC, parasitic extraction awareness, and signoff handoff quality.

Preferred Qualifications
  • Experience with HBM / DRAM adjacent SoC designs, or memory-subsystem-heavy SoCs.
  • Bachelor's or master's degree in electrical engineering, Computer Engineering, or a related field.
  • Minimum 10 years of experience in a related field.
  • Proven ability to mentor and develop engineers early in their careers.

As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on micron.com/careers/benefits.
Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.
To learn about your right to work click here.
To learn more about Micron, please visit micron.com/careers
For US Sites Only: To request assistance with the application process and/or for reasonable accommodations, please contact Micron's People Organization at hrsupport_na@micron.com or 1-800-336-8918 (select option #3)
Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.
Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.
AI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.
Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.

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