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Principal Physical Design Engineer Jobs (NOW HIRING)

Marvell

Principal Physical Design Engineer

Westborough, MA · On-site

$140.10K - $144.20K/yr

Collaborate crossfunctionally to influence design decisions, constraints, and microarchitecture choices that improve physical feasibility * Guide and mentor junior engineers , sharing best practices ...

Baya Systems

Physical Design Engineer

Santa Clara, CA

$159.70K - $164.40K/yr

Physical Design Engineer Location: Santa Clara, CA About the role: We are seeking a seasoned Physical Design Engineer with a strong background in all aspects of Physical Design and Implementation ...

K2 Space

OR

$190K - $280K/yr

The Role We are looking for a Principal ASIC Physical Design Engineer to lead the implementation of complex SoCs for next-generation satellite and space systems. You will own the full physical design ...

Apple

Physical Design Engineer

Cupertino, CA · On-site

$167.80K - $172.70K/yr

We have an opportunity for a forward-thinking and unusually hardworking Physical Design Engineer. As a member of our wide-ranging group, you will have the rare and great opportunity to craft upcoming ...

Apple

Physical Design Engineer

Beaverton, OR

$141.50K - $145.70K/yr

We have an opportunity for a forward-thinking and unusually hardworking Physical Design Engineer. As a member of our wide-ranging group, you will have the rare and great opportunity to craft upcoming ...

Apple

Physical Design Engineer

San Francisco, CA · On-site

$160.20K - $164.90K/yr

We have an opportunity for a forward-thinking and unusually hardworking Physical Design Engineer. As a member of our wide-ranging group, you will have the rare and great opportunity to craft upcoming ...

Apple

Physical Design Engineer

Cupertino, CA · On-site

$167.80K - $172.70K/yr

We have an opportunity for a forward-thinking and unusually hardworking Physical Design Engineer. As a member of our wide-ranging group, you will have the rare and great opportunity to craft upcoming ...

Apple

Physical Design Engineer

Cupertino, CA · On-site

$167.80K - $172.70K/yr

We have an opportunity for a forward-thinking and unusually hardworking Physical Design Engineer. As a member of our wide-ranging group, you will have the rare and great opportunity to craft upcoming ...

Apple

Physical Design Engineer

Cupertino, CA · On-site

$167.80K - $172.70K/yr

We have an opportunity for a forward-thinking and unusually hardworking Physical Design Engineer. As a member of our wide-ranging group, you will have the rare and great opportunity to craft upcoming ...

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Principal Physical Design Engineer information

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$74K

$147.2K

$212.5K

How much do principal physical design engineer jobs pay per year?

As of May 31, 2026, the average yearly pay for principal physical design engineer in the United States is $147,220.00, according to ZipRecruiter salary data. Most workers in this role earn between $118,500.00 and $173,000.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a Principal Physical Design Engineer, and why are they important?

To thrive as a Principal Physical Design Engineer, you need deep expertise in ASIC/FPGA physical design, strong knowledge of RTL-to-GDSII flow, and a relevant degree in electrical or computer engineering. Proficiency with EDA tools such as Synopsys, Cadence, or Mentor Graphics, as well as familiarity with scripting languages and industry-standard verification methodologies, is essential. Exceptional problem-solving, leadership, and communication skills help drive complex projects and collaborate across cross-functional teams. These skills are crucial to ensure optimal chip performance, timely delivery, and successful integration within advanced semiconductor development environments.

What are some typical challenges faced by Principal Physical Design Engineers when managing complex chip development projects?

Principal Physical Design Engineers often navigate challenges such as balancing power, performance, and area (PPA) requirements while meeting tight project deadlines. They must coordinate across multiple teams, including logic design and verification, to resolve integration issues and ensure that design constraints are met. Additionally, they frequently address timing closure and signal integrity concerns, requiring advanced problem-solving and project management skills. The role demands staying current with EDA tools and process technologies to drive innovation and efficiency in chip design workflows.

What are Principal Physical Design Engineers?

Principal Physical Design Engineers are senior professionals in the semiconductor industry responsible for overseeing the physical implementation of integrated circuit (IC) designs. They lead teams in tasks like floorplanning, placement, routing, timing closure, and verification to ensure that chip layouts meet performance, power, and area requirements. These engineers use specialized design tools and collaborate closely with other engineering teams throughout the chip development process. Their expertise is crucial for translating circuit schematics into manufacturable silicon.

What is the difference between Principal Physical Design Engineer vs Physical Design Engineer?

AspectPrincipal Physical Design EngineerPhysical Design Engineer
CredentialsBachelor's/Master's in Electrical Engineering or related; extensive experienceBachelor's/Master's in Electrical Engineering or related; some experience
Work EnvironmentLead design teams, oversee complex chip layouts, strategic planningImplement physical design tasks, optimize layouts, follow design flows
Industry UsageUsed in advanced semiconductor companies, high-level design rolesCommon in semiconductor companies, entry to mid-level roles

The Principal Physical Design Engineer typically holds a senior role with leadership responsibilities, overseeing complex projects and guiding teams. In contrast, a Physical Design Engineer focuses on executing physical design tasks under supervision. Both roles require similar technical skills and industry experience, but the principal position involves strategic planning and higher-level decision-making.

More about Principal Physical Design Engineer jobs
What job categories do people searching Principal Physical Design Engineer jobs look for? The top searched job categories for Principal Physical Design Engineer jobs are:
Principal Physical Design Engineer jobs near you
Infographic showing various Principal Physical Design Engineer job openings in the United States as of May 2026, with employment types broken down into 1% As Needed, 98% Full Time, and 1% Part Time. Highlights an 88% Physical, 1% Hybrid, and 11% Remote job distribution, with an average salary of $147,220 per year, or $70.8 per hour.

Principal Physical Design Engineer

Hewlett Packard Enterprise Development LP

Sunnyvale, CA • On-site

$159.60K - $164.30K/yr

Full-time

This job post has expired today. Applications are no longer accepted.

Job description

Principal Physical Design Engineer
This role has been designed as 'Hybrid' with an expectation that you will work on average 2 days per week from an HPE office.
Who We Are:
Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today's complex world. Our culture thrives on finding new and better ways to accelerate what's next. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good. If you are looking to stretch and grow your career our culture will embrace you. Open up opportunities with HPE.
Job Description:
SoC Top-Level & block-level Physical Design Engineer
As a block-level and top-level SOC Physical Design Engineer, you will contribute to all phases of physical design from RTL to the delivery of our final GDSII. Your responsibilities include:
Responsibilities:
  • Implement physical design at the large SoC chip level from RTL to GDSII, creating a design database ready for manufacturing.

  • Interact with IP vendors to understand IP integration requirements and integrate all blocks, IPs, and sub-chips at a large SoC level.

  • Collaborate with the packaging team on Microbump/Probe Bump/Bump/Pad placement.

  • Build full chip floorplan, including pads/ports/bump placement, block placement and optimization, block pins placement and alignment, power grid, and RDL design, etc.

  • Develop the chip-level clock network and clock stations in collaboration with clock experts.

  • Budget timing among blocks and sub-chips at the chip level, generating block/chip-level static timing constraints.

  • Arrange, analyze, and optimize feedthrough and repeaters among all blocks/sub-chips at the chip level.

  • Perform block-level place and route, including custom place & route, ensuring the design meets timing, area, power constraints, and all sign-off criteria.

  • Generate and implement ECOs to fix timing, signal integrity, EM/IR violations, PV, and complete formal verification.

  • Integrate DFT into physical design, ensuring alignment with overall test strategies and manufacturing requirements.

  • Run Physical Design verification flow at chip/block level, fixing LVS/DRC/ERC/ANT violations.

  • Collaborate closely with architecture, frontend design, DV, and package teams to ensure cohesive design implementation and successful project tapeouts.

Minimum Qualifications:
Education:
  • BS degree in electrical engineering, computer engineering, or a related field with 7+ years of experience in block or full-chip physical design, or

  • MS degree in the above fields with 5+ years of related experience.

Technical Expertise:
  • Deep design experience in large SoC designs, including IP integration, padring design, bump planning, and RDL routing strategy.

  • Extensive knowledge and practices in Physical Design, including physically aware synthesis, floor-planning, place & route, CTS, and repeater/feedthrough.

  • Experience in developing and implementing power-grid and clock network at chip level.

  • Knowledge of basic SoC architecture and HDL languages like Verilog to work with the logic design team for timing fixes.

  • Experience in physical design verification to debug LVS/DRC/ERC/ANT issues at chip/block level.

  • Experience in custom place and route.

  • Exposure to 2.5D/3D packaging is preferred.

  • High performance and large chip design experience is preferred.

  • Exposure to DFT is preferred.

  • Proficiency in writing Linux shell scripts in Perl, TCL, and Python.

  • Real chip tapeout experience in 7nm and/or below with a successful signoff track record.

  • Self-motivated with strong problem-solving and debugging skills.

  • Ability to work effectively in a dynamic group environment.

What We Can Offer You:
Health & Wellbeing
We strive to provide our team members and their loved ones with a comprehensive suite of benefits that supports their physical, financial and emotional wellbeing.
Personal & Professional Development
We also invest in your career because the better you are, the better we all are. We have specific programs catered to helping you reach any career goals you have - whether you want to become a knowledge expert in your field or apply your skills to another division.
Unconditional Inclusion
We are unconditionally inclusive in the way we work and celebrate individual uniqueness. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good.
Let's Stay Connected:
Follow @HPECareers on Instagram to see the latest on people, culture and tech at HPE.
#unitedstates
Job:
Engineering
Job Level:
TCP_05
"The expected salary/wage range for this position is provided below. Actual offer may vary from this range based upon geographic location, work experience, education/training, and/or skill level.
- United States of America: Annual Salary USD 174,000 - 352,500 in California
The listed salary range reflects base salary. Variable incentives may also be offered."
Information about employee benefits offered in the US can be found at https://myhperewards.com/main/new-hire-enrollment.html
HPE is an Equal Employment Opportunity/ Veterans/Disabled/LGBT employer. We do not discriminate on the basis of race, gender, or any other protected category, and all decisions we make are made on the basis of qualifications, merit, and business need. Our goal is to be one global team that is representative of our customers, in an inclusive environment where we can continue to innovate and grow together. Please click here: Equal Employment Opportunity.
Hewlett Packard Enterprise is EEO Protected Veteran/ Individual with Disabilities.
HPE will comply with all applicable laws related to employer use of arrest and conviction records, including laws requiring employers to consider for employment qualified applicants with criminal histories.
No Fees Notice & Recruitment Fraud Disclaimer
It has come to HPE's attention that there has been an increase in recruitment fraud whereby scammer impersonate HPE or HPE-authorized recruiting agencies and offer fake employment opportunities to candidates. These scammers often seek to obtain personal information or money from candidates.
Please note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge any candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process. The credentials of any hiring agency that claims to be working with HPE for recruitment of talent should be verified by candidates and candidates shall be solely responsible to conduct such verification. Any candidate/individual who relies on the erroneous representations made by fraudulent employment agencies does so at their own risk, and HPE disclaims liability for any damages or claims that may result from any such communication.

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