Physical Design Engineer
$139K - $143K/yr
Overall, 7 to 12 yrs of exp as a Physical Design Engineer. (Remote Opening) Must Have : Advance Node Exp 3nm/5nm,Full Chip Integration, Advance/Complex SOC Integration, Cadence/Synopsys (Innovus ...
Physical Design Engineer
$139K - $143K/yr
Overall, 7 to 12 yrs of exp as a Physical Design Engineer. (Remote Opening) Must Have : Advance Node Exp 3nm/5nm,Full Chip Integration, Advance/Complex SOC Integration, Cadence/Synopsys (Innovus ...
Staff Physical Design Engineer
Richardson, TX · On-site
$123K - $127K/yr
May telecommute part-time. Employer will accept a Bachelor's degree in Electronics Engineering ... Position requires: 1. Digital design; 2. Physical design; 3. Layout design; 4. Timing Closure; 5. ...
Staff Physical Design Engineer
Richardson, TX · On-site
$123K - $127K/yr
May telecommute part-time. Employer will accept a Bachelor's degree in Electronics Engineering ... Position requires: 1. Digital design; 2. Physical design; 3. Layout design; 4. Timing Closure; 5. ...
Circuits Physical Design Engineer - Library/Process Monitor
Beaverton, OR · On-site
$141K - $145K/yr
We have an extraordinary opportunity for Physical Design Engineers. In this highly visible role, you will be at the heart of a processor design effort, working with foundation IP developers on ...
Circuits Physical Design Engineer - Library/Process Monitor
Beaverton, OR · On-site
$141K - $145K/yr
We have an extraordinary opportunity for Physical Design Engineers. In this highly visible role, you will be at the heart of a processor design effort, working with foundation IP developers on ...
We have an extraordinary opportunity for Physical Design Engineers. In this highly visible role, you will be at the heart of a processor design effort, working with foundation IP developers on ...
We have an extraordinary opportunity for Physical Design Engineers. In this highly visible role, you will be at the heart of a processor design effort, working with foundation IP developers on ...
We have an extraordinary opportunity for Physical Design Engineers. In this highly visible role, you will be at the heart of a processor design effort, working with foundation IP developers on ...
We have an extraordinary opportunity for Physical Design Engineers. In this highly visible role, you will be at the heart of a processor design effort, working with foundation IP developers on ...
Engineer, ASIC Physical Design
Minneapolis, MN · On-site
$142K - $176K/yr
Chip floor-planning, physical design, IP integration, static timing analysis, design validation ... May telecommute part-time. Employer will accept a Master's degree in Electrical Engineering ...
Engineer, ASIC Physical Design
Minneapolis, MN · On-site
$142K - $176K/yr
Chip floor-planning, physical design, IP integration, static timing analysis, design validation ... May telecommute part-time. Employer will accept a Master's degree in Electrical Engineering ...
Cellular ASIC Design Engineer
$175K - $308K/yr
... physical design teams on timing closure, collaborating with CAD teams, IP teams and Design ... programming skills (Python, Perl, TCL, Unix shell, C/C++) for methodology automation and ...
Cellular ASIC Design Engineer
$175K - $308K/yr
... physical design teams on timing closure, collaborating with CAD teams, IP teams and Design ... programming skills (Python, Perl, TCL, Unix shell, C/C++) for methodology automation and ...
Cellular ASIC Design Engineer
$175K - $308K/yr
... physical design teams on timing closure, collaborating with CAD teams, IP teams and Design ... programming skills (Python, Perl, TCL, Unix shell, C/C++) for methodology automation and ...
Cellular ASIC Design Engineer
$175K - $308K/yr
... physical design teams on timing closure, collaborating with CAD teams, IP teams and Design ... programming skills (Python, Perl, TCL, Unix shell, C/C++) for methodology automation and ...
Cellular ASIC Design Engineer
$175K - $308K/yr
... physical design teams on timing closure, collaborating with CAD teams, IP teams and Design ... programming skills (Python, Perl, TCL, Unix shell, C/C++) for methodology automation and ...
Cellular ASIC Design Engineer
$175K - $308K/yr
... physical design teams on timing closure, collaborating with CAD teams, IP teams and Design ... programming skills (Python, Perl, TCL, Unix shell, C/C++) for methodology automation and ...
Physical Design Lead, ASIC
Sunnyvale, CA · On-site
$159K - $164K/yr
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. * 10 years of experience in physical design, including ...
Physical Design Lead, ASIC
Sunnyvale, CA · On-site
$159K - $164K/yr
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. * 10 years of experience in physical design, including ...
Cellular ASIC Design Engineer
Austin, TX · On-site
Description As a Cellular ASIC Design Engineer, you'll develop and optimize design and ... Preferred Qualifications Solid understanding of Physical Design challenges, proficiency with ...
Cellular ASIC Design Engineer
Austin, TX · On-site
Description As a Cellular ASIC Design Engineer, you'll develop and optimize design and ... Preferred Qualifications Solid understanding of Physical Design challenges, proficiency with ...
Electrical Engineer (Part-time)
Elgin, IL · On-site
$25 - $30/hr
Electrical Engineer (Part-time) Blue Collar Location: Elgin, IL. 60123 Shift Hours: 8:00 am - 2:00 ... Responsibilities - Design and develop electrical systems and components for various projects ...
Electrical Engineer (Part-time)
Elgin, IL · On-site
$25 - $30/hr
Electrical Engineer (Part-time) Blue Collar Location: Elgin, IL. 60123 Shift Hours: 8:00 am - 2:00 ... Responsibilities - Design and develop electrical systems and components for various projects ...
Be an active participant in preparing and presenting content for design reviews with the HLS ... physical proximity to other people All qualified candidates will receive consideration for all ...
Be an active participant in preparing and presenting content for design reviews with the HLS ... physical proximity to other people All qualified candidates will receive consideration for all ...
Design Engineer
Mission Viejo, CA · Remote
$30 - $50/hr
Saratech is seeking a part-time Design Engineer. You will assist the Engineering Services/Design ... Physical demands: * Follow detailed complex directions, reason and problem solve. * The person will ...
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Design Engineer
Mission Viejo, CA · Remote
$30 - $50/hr
Saratech is seeking a part-time Design Engineer. You will assist the Engineering Services/Design ... Physical demands: * Follow detailed complex directions, reason and problem solve. * The person will ...
Design Engineer
$30 - $50/hr
Saratech is seeking a part-time Design Engineer. You will assist the Engineering Services/Design ... Physical demands: * Follow detailed complex directions, reason and problem solve. * The person will ...
Design Engineer
$30 - $50/hr
Saratech is seeking a part-time Design Engineer. You will assist the Engineering Services/Design ... Physical demands: * Follow detailed complex directions, reason and problem solve. * The person will ...
Design Engineer
Mission Viejo, CA · On-site
$30 - $50/hr
Saratech is seeking a part-time Design Engineer. You will assist the Engineering Services/Design ... Physical demands: * Follow detailed complex directions, reason and problem solve. * The person will ...
Design Engineer
Mission Viejo, CA · On-site
$30 - $50/hr
Saratech is seeking a part-time Design Engineer. You will assist the Engineering Services/Design ... Physical demands: * Follow detailed complex directions, reason and problem solve. * The person will ...
Experience with the design, assembly, verification, testing, and operation of Space system hardware ... physical proximity to other people All qualified candidates will receive consideration for all ...
Experience with the design, assembly, verification, testing, and operation of Space system hardware ... physical proximity to other people All qualified candidates will receive consideration for all ...
CPU Physical Design Timing Engineer (Austin, TX)
Austin, TX · On-site
$134K - $138K/yr
As a CPU Physical Design Timing Engineer, you will work with microarchitecture and RTL design team to develop timing constraints, drive implementation of the designs to meet aggressive power, area ...
CPU Physical Design Timing Engineer (Austin, TX)
Austin, TX · On-site
$134K - $138K/yr
As a CPU Physical Design Timing Engineer, you will work with microarchitecture and RTL design team to develop timing constraints, drive implementation of the designs to meet aggressive power, area ...
The substation Physical design deliverables include general arrangement drawings, electrical ... Employment Type: PART_TIME
The substation Physical design deliverables include general arrangement drawings, electrical ... Employment Type: PART_TIME
Utilizes knowledge of various processes, engineering practices, mathematics, building materials, and other physical sciences to complete drawings * Apply engineering principles to design and ...
Utilizes knowledge of various processes, engineering practices, mathematics, building materials, and other physical sciences to complete drawings * Apply engineering principles to design and ...
Physical Design Engineer Parttime information
See salary details
$95K - $99.2K
0% of jobs
$99.2K - $103.5K
0% of jobs
$103.5K - $107.7K
0% of jobs
$107.7K - $111.9K
0% of jobs
$111.9K - $116.1K
0% of jobs
$116.1K - $120.4K
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$120.4K - $124.6K
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$124.6K - $128.8K
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$128.8K - $133K
1% of jobs
$135.4K is the 25th percentile. Wages below this are outliers.
$133K - $137.3K
43% of jobs
The median wage is $137.7K / yr.
$137.3K - $141.5K
56% of jobs
$95K
$141.5K
How much do physical design engineer parttime jobs pay per year?
As of Jul 11, 2026, the average yearly pay for physical design engineer parttime in the United States is $139,408.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $140,000.00 per year, depending on experience, location, and employer.
What is the difference between Physical Design Engineer Parttime vs Physical Design Engineer?
| Aspect | Physical Design Engineer Parttime | Physical Design Engineer |
|---|---|---|
| Work Hours | Part-time, fewer hours per week | Full-time, standard hours |
| Responsibilities | Assists in physical design tasks, limited scope | Leads entire physical design process from synthesis to tape-out |
| Credentials | Bachelor's or Master's in EDA, VLSI design | Similar credentials, often with more experience |
| Work Environment | Typically remote or flexible | On-site or hybrid in design teams |
Physical Design Engineer Parttime roles focus on supporting specific tasks with flexible hours, while full-time Physical Design Engineers handle comprehensive design responsibilities. Both roles require similar educational backgrounds and skills, but differ mainly in work hours and scope of responsibilities.
More about Physical Design Engineer Parttime jobs
What cities are hiring for Physical Design Engineer Parttime jobs? Cities with the most Physical Design Engineer Parttime job openings:
What states have the most Physical Design Engineer Parttime jobs? States with the most job openings for Physical Design Engineer Parttime jobs include:
What job categories do people searching Physical Design Engineer Parttime jobs look for? The top searched job categories for Physical Design Engineer Parttime jobs are:
$139K - $143K/yr
Part-time
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Job description
Job Description:
Overall, 7 to 12 yrs of exp as a Physical Design Engineer. (Remote Opening)
Must Have : Advance Node Exp 3nm/5nm,Full Chip Integration, Advance/Complex SOC Integration, Cadence/Synopsys (Innovus, ICC2).
Overall, 7 to 12 yrs of exp as a Physical Design Engineer. (Remote Opening)
Must Have : Advance Node Exp 3nm/5nm,Full Chip Integration, Advance/Complex SOC Integration, Cadence/Synopsys (Innovus, ICC2).
- In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floorplanning, Power Grid Design, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification, Chip finishing. Should have experience on Physical Design Methodologies and sub-micron technology of 7nm and lower technology nodes.
- Must have hands-on experience on PnR Suite from Synopsys/Cadence(Innovus, ICC2).
- Strong experience on Static Timing Analysis(PrimeTime - SI), EM/IR-Drop analysis (PT-PX, Redhawk), Physical Verification(Calibre).
- Understanding the practical application of methodologies and Physical Design Tools, Flow Automation and Improvements.
- Experience in complex SOC integration, Low Power and High Speed Design and Advanced Physical Verification Techniques.
- Good Customer interaction, Communication and Teamwork skills.
- Should have experience in handling >5M instance count, 1.5GHz frequency designs.
- Good to have experience on programming in Tcl/Tk/Perl to automate design process and improve efficiency.