Physical Design Engineer
$139K - $143K/yr
Overall, 7 to 12 yrs of exp as a Physical Design Engineer. (Remote Opening) Must Have : Advance Node Exp 3nm/5nm,Full Chip Integration, Advance/Complex SOC Integration, Cadence/Synopsys (Innovus ...
$139K - $143K/yr
Overall, 7 to 12 yrs of exp as a Physical Design Engineer. (Remote Opening) Must Have : Advance Node Exp 3nm/5nm,Full Chip Integration, Advance/Complex SOC Integration, Cadence/Synopsys (Innovus ...
$139K - $143K/yr
Overall, 7 to 12 yrs of exp as a Physical Design Engineer. (Remote Opening) Must Have : Advance Node Exp 3nm/5nm,Full Chip Integration, Advance/Complex SOC Integration, Cadence/Synopsys (Innovus ...
Westford, MA · On-site
$141K - $145K/yr
NVIDIA is looking for best-in-class Senior Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices ...
Westford, MA · On-site
$141K - $145K/yr
NVIDIA is looking for best-in-class Senior Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices ...
Cannon Falls, MN · On-site
We are seeking a motivated and detail-oriented Design Engineer to join our team. This role is responsible for designing and developing innovative products that meet customer requirements while ...
Cannon Falls, MN · On-site
We are seeking a motivated and detail-oriented Design Engineer to join our team. This role is responsible for designing and developing innovative products that meet customer requirements while ...
Richardson, TX · On-site
$123K - $127K/yr
May telecommute part-time. Employer will accept a Bachelor's degree in Electronics Engineering ... Position requires: 1. Digital design; 2. Physical design; 3. Layout design; 4. Timing Closure; 5. ...
Richardson, TX · On-site
$123K - $127K/yr
May telecommute part-time. Employer will accept a Bachelor's degree in Electronics Engineering ... Position requires: 1. Digital design; 2. Physical design; 3. Layout design; 4. Timing Closure; 5. ...
Beaverton, OR · On-site
$141K - $145K/yr
We have an extraordinary opportunity for Physical Design Engineers. In this highly visible role, you will be at the heart of a processor design effort, working with foundation IP developers on ...
Beaverton, OR · On-site
$141K - $145K/yr
We have an extraordinary opportunity for Physical Design Engineers. In this highly visible role, you will be at the heart of a processor design effort, working with foundation IP developers on ...
We have an extraordinary opportunity for Physical Design Engineers. In this highly visible role, you will be at the heart of a processor design effort, working with foundation IP developers on ...
We have an extraordinary opportunity for Physical Design Engineers. In this highly visible role, you will be at the heart of a processor design effort, working with foundation IP developers on ...
We have an extraordinary opportunity for Physical Design Engineers. In this highly visible role, you will be at the heart of a processor design effort, working with foundation IP developers on ...
We have an extraordinary opportunity for Physical Design Engineers. In this highly visible role, you will be at the heart of a processor design effort, working with foundation IP developers on ...
San Diego, CA · On-site
Cellular Asic Design Engineer Work Locations (3) Submit Resume Apple is where individual ... Experience with Physical Design challenges, proficiency with synthesis, place and route tools, and ...
San Diego, CA · On-site
Cellular Asic Design Engineer Work Locations (3) Submit Resume Apple is where individual ... Experience with Physical Design challenges, proficiency with synthesis, place and route tools, and ...
Austin, TX · On-site
Cellular Asic Design Engineer Work Locations (3) Submit Resume Apple is where individual ... Experience with Physical Design challenges, proficiency with synthesis, place and route tools, and ...
Austin, TX · On-site
Cellular Asic Design Engineer Work Locations (3) Submit Resume Apple is where individual ... Experience with Physical Design challenges, proficiency with synthesis, place and route tools, and ...
Minneapolis, MN · On-site
$142K - $176K/yr
Chip floor-planning, physical design, IP integration, static timing analysis, design validation ... May telecommute part-time. Employer will accept a Master's degree in Electrical Engineering ...
Minneapolis, MN · On-site
$142K - $176K/yr
Chip floor-planning, physical design, IP integration, static timing analysis, design validation ... May telecommute part-time. Employer will accept a Master's degree in Electrical Engineering ...
San Jose, CA · On-site
$159K - $164K/yr
We are looking for a Senior/Staff STA Engineer to lead full-chip timing signoff activities for ... This role requires close collaboration with RTL, Physical Design, Clocking, to achieve timing ...
San Jose, CA · On-site
$159K - $164K/yr
We are looking for a Senior/Staff STA Engineer to lead full-chip timing signoff activities for ... This role requires close collaboration with RTL, Physical Design, Clocking, to achieve timing ...
$201K - $367K/yr
... physical design teams on timing closure, collaborating with CAD teams, IP teams and Design ... programming skills (Python, Perl, TCL, Unix shell, C/C++) for methodology automation and ...
$201K - $367K/yr
... physical design teams on timing closure, collaborating with CAD teams, IP teams and Design ... programming skills (Python, Perl, TCL, Unix shell, C/C++) for methodology automation and ...
$201K - $367K/yr
... physical design teams on timing closure, collaborating with CAD teams, IP teams and Design ... programming skills (Python, Perl, TCL, Unix shell, C/C++) for methodology automation and ...
$201K - $367K/yr
... physical design teams on timing closure, collaborating with CAD teams, IP teams and Design ... programming skills (Python, Perl, TCL, Unix shell, C/C++) for methodology automation and ...
$171K - $302K/yr
... physical design teams on timing closure, collaborating with CAD teams, IP teams and Design ... programming skills (Python, Perl, TCL, Unix shell, C/C++) for methodology automation and ...
$171K - $302K/yr
... physical design teams on timing closure, collaborating with CAD teams, IP teams and Design ... programming skills (Python, Perl, TCL, Unix shell, C/C++) for methodology automation and ...
$201K - $367K/yr
... physical design teams on timing closure, collaborating with CAD teams, IP teams and Design ... programming skills (Python, Perl, TCL, Unix shell, C/C++) for methodology automation and ...
$201K - $367K/yr
... physical design teams on timing closure, collaborating with CAD teams, IP teams and Design ... programming skills (Python, Perl, TCL, Unix shell, C/C++) for methodology automation and ...
$171K - $302K/yr
... physical design teams on timing closure, collaborating with CAD teams, IP teams and Design ... programming skills (Python, Perl, TCL, Unix shell, C/C++) for methodology automation and ...
$171K - $302K/yr
... physical design teams on timing closure, collaborating with CAD teams, IP teams and Design ... programming skills (Python, Perl, TCL, Unix shell, C/C++) for methodology automation and ...
$171K - $302K/yr
... physical design teams on timing closure, collaborating with CAD teams, IP teams and Design ... programming skills (Python, Perl, TCL, Unix shell, C/C++) for methodology automation and ...
$171K - $302K/yr
... physical design teams on timing closure, collaborating with CAD teams, IP teams and Design ... programming skills (Python, Perl, TCL, Unix shell, C/C++) for methodology automation and ...
Austin, TX · On-site
As a Cellular ASIC Design Engineer, you'll develop and optimize design and implementation ... Experience with Physical Design challenges, proficiency with synthesis, place and route tools, and ...
Austin, TX · On-site
As a Cellular ASIC Design Engineer, you'll develop and optimize design and implementation ... Experience with Physical Design challenges, proficiency with synthesis, place and route tools, and ...
Santa Clara, CA · On-site
$159K - $164K/yr
As a CPU Physical Design Timing Engineer, you will work with microarchitecture and RTL design team to develop timing constraints, drive implementation of the designs to meet aggressive power, area ...
Santa Clara, CA · On-site
$159K - $164K/yr
As a CPU Physical Design Timing Engineer, you will work with microarchitecture and RTL design team to develop timing constraints, drive implementation of the designs to meet aggressive power, area ...
Santa Clara, CA · On-site
$159K - $164K/yr
As a CPU Physical Design Timing Engineer, you will work with microarchitecture and RTL design team to develop timing constraints, drive implementation of the designs to meet aggressive power, area ...
Santa Clara, CA · On-site
$159K - $164K/yr
As a CPU Physical Design Timing Engineer, you will work with microarchitecture and RTL design team to develop timing constraints, drive implementation of the designs to meet aggressive power, area ...
$95K - $99.2K
0% of jobs
$99.2K - $103.5K
0% of jobs
$103.5K - $107.7K
0% of jobs
$107.7K - $111.9K
0% of jobs
$111.9K - $116.1K
0% of jobs
$116.1K - $120.4K
0% of jobs
$120.4K - $124.6K
0% of jobs
$124.6K - $128.8K
0% of jobs
$128.8K - $133K
1% of jobs
$135.4K is the 25th percentile. Wages below this are outliers.
$133K - $137.3K
43% of jobs
The median wage is $137.7K / yr.
$137.3K - $141.5K
56% of jobs
$95K
$141.5K
| Aspect | Physical Design Engineer Part Time | Digital Design Engineer Part Time |
|---|---|---|
| Primary Focus | Physical implementation, layout, timing, and power optimization | Digital logic design, HDL coding, simulation, and verification |
| Skills & Certifications | VLSI design, EDA tools, CMOS fabrication knowledge | HDL languages (Verilog/VHDL), simulation tools, FPGA/ASIC design |
| Work Environment | Semiconductor companies, chip design firms, hardware labs | Semiconductor companies, FPGA/ASIC design teams, electronics firms |
Physical Design Engineer Part Time and Digital Design Engineer Part Time share overlapping skills in semiconductor industry environments, but differ mainly in their focus areas. Physical Design Engineers concentrate on layout and physical implementation, while Digital Design Engineers focus on logic design and HDL coding. Both roles often require similar certifications and work in related settings, making them common comparison points for part-time roles in chip design.
$139K - $143K/yr
Part-time
Posted 18 days ago