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Vlsi Dft Jobs (NOW HIRING)

Retym

VLSI Design Engineer

Austin, TX · On-site

$134K - $138K/yr

As an VLSI Digital Design Engineer/Micro-architect, you'll have the opportunity to design highly ... DFT team: Ensure design is scan-insertable, supports ATPG, BIST, etc. * Backend/Physical design ...

Retym

DFT Tech Lead

Austin, TX · On-site

As a DFT Tech Lead you will work closely with all other design teams - backend, vlsi, verification and analog, fully responsible for defining, implementing, and deploying advanced design-for-test ...

Wipro Limited

DFT Engineer

Mountain View, CA · On-site

$45K - $121K/yr

  • Medical

  • Dental

  • PTO

DFT Engineer City: Mountain View State/Province: California Posting Start Date: 7/21/26 Wipro ... VLSI Physical Place and Route. Experience: 3-5 Years. The expected compensation for this role ...

Broadcom Inc.

Senior Digital VLSI Design Engineer

Fort Collins, CO · On-site

$121.90 - $195/hr

  • Medical

  • Dental

  • Vision

  • Retirement

  • PTO

We are seeking a Senior Digital VLSI Design Engineer with deep expertise in Synthesis, DFT, Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC) sign‑off for high speed complex IPs to be ...

Nvidia

Senior DFT Engineer

Santa Clara, CA · On-site

$122K - $168K/yr

Collaborate closely with VLSI and Product Engineering groups to design innovative DFT approaches that advance silicon test technology. * Lead end-to-end planning and timely execution of NVIDIA's new ...

Nvidia Corporation

Senior DFT Engineer

Santa Clara, CA · On-site

$122K - $168K/yr

Collaborate closely with VLSI and Product Engineering groups to design innovative DFT approaches that advance silicon test technology. * Lead end-to-end planning and timely execution of NVIDIA's new ...

Qualcomm

CPU DFT Engineer

Santa Clara, CA · On-site

$142K - $213K/yr

As a DFT Engineer you will work with chip architects, chip designers, implementation engineers and ... and digital VLSI designs. Then you'll insure it becomes reality. We're doing a ground up ...

Broadcom

Senior Digital VLSI Design Engineer

Fort Collins, CO · On-site

  • Medical

  • Dental

  • Vision

  • Retirement

  • PTO

We are seeking a Senior Digital VLSI Design Engineer with deep expertise in Synthesis, DFT, Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC) sign-off for high speed complex IPs to be ...

Broadcom

Senior Digital VLSI Design Engineer

San Jose, CA

  • Medical

  • Dental

  • Vision

  • Retirement

  • PTO

We are seeking a Senior Digital VLSI Design Engineer with deep expertise in Synthesis, DFT, Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC) sign-off for high speed complex IPs to be ...

Nvidia

Senior DFT Engineer

Santa Clara, CA · Hybrid

$122K - $168K/yr

Co-architect novel DFT strategies alongside VLSI and Product Engineering teams to push the boundaries of silicon test innovation. * Own the full ATPG lifecycle-verification, coverage analysis ...

Nvidia Corporation

Senior DFT Engineer

Santa Clara, CA · On-site

$122K - $168K/yr

Co-architect novel DFT strategies alongside VLSI and Product Engineering teams to push the boundaries of silicon test innovation. * Own the full ATPG lifecycle-verification, coverage analysis ...

Qualcomm

Synthesis-DFT Stitch CAD Engineer

San Diego, CA · On-site

$164K - $246K/yr

... in VLSI CAD, preferably Synthesis, DFT and P&R •     5-10 years of experience with ... scripting tools and programming languages: Python and TCL preferred. Principal Duties and ...

Nvidia

Senior DFT Power Methodology Engineer

Santa Clara, CA · On-site

$122K - $168K/yr

Understanding of fundamental DFT topics and VLSI areas of power, timing & voltage noise * Experience in Power Analysis, Thermal Analysis & IR Drop tools is a plus. * Experience in application of AI ...

Nvidia

Senior DFT Power Methodology Engineer

Santa Clara, CA · On-site

$122K - $168K/yr

Understanding of fundamental DFT topics and VLSI areas of power, timing & voltage noise * Experience in Power Analysis, Thermal Analysis & IR Drop tools is a plus. * Experience in application of AI ...

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How much do vlsi dft jobs pay per hour?

As of Aug 14, 2026, the average hourly pay for vlsi dft in the United States is $31.52, according to ZipRecruiter salary data. Most workers in this role earn between $25.72 and $35.34 per hour, depending on experience, location, and employer.

Is Vlsi Dft a good career?

VLSI DFT (Design for Testability) is a specialized field within semiconductor design that focuses on making integrated circuits easier to test and verify. It offers opportunities in the semiconductor industry, requiring skills in digital design, testing methodologies, and EDA tools. The career can be stable and rewarding for those with technical expertise and an interest in hardware design and testing processes.

What is a VLSI DFT?

A VLSI DFT (Design for Test) job involves designing and implementing testability features in integrated circuits to ensure efficient manufacturing testing and fault detection. Engineers work on techniques like scan chains, built-in self-test (BIST), boundary scan, and automatic test pattern generation (ATPG) to improve chip test coverage and reliability. Their role helps identify manufacturing defects and optimize testing costs while ensuring high-quality silicon.

What are the key skills and qualifications needed to thrive in the VLSI DFT position, and why are they important?

To thrive as a VLSI DFT (Design-for-Test) engineer, you need a solid background in digital design, test methodologies, and a relevant degree such as Electrical or Electronics Engineering. Proficiency with EDA tools like Synopsys DFT Compiler, Tessent, or Cadence, along with a good understanding of scripting languages and industry-standard protocols, is typically required. Strong problem-solving abilities, attention to detail, and effective communication are vital soft skills in this role. These competencies are crucial for designing efficient, testable chips and collaborating with cross-functional teams to ensure product quality and manufacturability.

What are some typical challenges faced by VLSI DFT engineers, and how can candidates best prepare for them?

VLSI DFT engineers often encounter challenges such as optimizing test coverage without impacting design performance, managing test data volume, and integrating test features into complex chip designs. Staying up-to-date with evolving industry standards and tools, along with strong analytical skills, can help overcome these hurdles. Candidates can best prepare by gaining hands-on experience with leading DFT tools, understanding scan insertion and ATPG methodologies, and collaborating closely with design and verification teams. Emphasizing continuous learning and adaptability will set you up for long-term success in this dynamic and highly technical field.

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Vlsi Dft jobs near you
Infographic showing various Vlsi Dft job openings in the United States as of August 2026, with employment types broken down into 33% Full Time, and 67% Contract. Highlights an 100% In-person job distribution, with an average salary of $65,566 per year, or $31.5 per hour.

VLSI Design Engineer

Retym

Austin, TX • On-site

$134K - $138K/yr

Full-time

Re-posted 27 days ago

Job description

Description
We are looking for talented and experienced VLSI Design Engineers/Micro-architects.
As an VLSI Digital Design Engineer/Micro-architect, you'll have the opportunity to design highly sophisticated, innovative new cutting edge communication systems from scratch.
Key Responsibilities for a VLSI Design Engineer:
Work closely with Algorithm and Architecture teams
  • Understand and translate high-level algorithmic requirements into efficient hardware implementations.

Learn and analyze relevant protocols and standards
  • Interpret protocol specifications (e.g., Ethernet, etc.) and apply them accurately in design.

Participate in all design stages:
  • Micro-architecture definition
  • RTL coding (using Verilog/SystemVerilog)
  • Synthesis-friendly coding and timing-aware design

Collaborate cross-functionally:
  • Verification team: For testbench development, debug support, and functional coverage closure.
  • DFT team: Ensure design is scan-insertable, supports ATPG, BIST, etc.
  • Backend/Physical design team: For floorplanning, timing closure, and routing feedback.

Participate in Design Reviews
  • Present and defend design decisions in peer and formal reviews.

Perform Synthesis and Timing Analysis
  • Generate synthesis constraints (SDC), run synthesis, and analyze timing reports.

Debug and Fix Functional/Timing Issues
  • Collaborate in post-silicon or pre-silicon debug; use waveforms, assertions, and logic analyzers.

Optimize for Area, Power, and Performance (PPA)
  • Identify bottlenecks and opportunities for improvement within RTL.

Documentation
  • Maintain clear design documentation for reusability and reference (e.g., micro-architecture specs, interface docs).

Contribute to IP/SoC Integration
  • Work on integrating design blocks into larger systems and handling system-level interfaces.

Participate in Silicon Bring-up and Validation (optional but valuable)
  • Support bring-up of first silicon and assist with post-silicon validation, if applicable.

Keep up-to-date with Industry Trends and Tools
  • Learn new EDA tools, languages, and methodologies (e.g., CDC, Linting, Formal Verification).

Requirements
Job requirements:
  • +5 years of experience as ASIC/VLSI digital design engineer
  • Strong Verilog/System-Verilog experience
  • Familiar with simulation tools/environments, verification methodologies
  • Strong team player, solid interpersonal skills
  • Entrepreneurial can-do attitude, self-motivated, able to work independently
  • BS/MS in EE/CE from lead universities

Background in one or more of the following domains is an advantage:
  • Familiar with advanced design practices (Clock/Voltage domain crossing, Low Power Design, DFT)
  • Design DSP of oriented blocks
  • Ethernet (100G and above)
  • Scripting experience using several of the following: Python, Perl, TCL

Apply