Austin, TX · On-site
$134K - $138K/yr
... DFT or clocking.Experience or coursework with digital logic design, RTL, DV (testing), CMOS transistor logics or VLSI concepts.Experience with scripting languages such as TCL, Python, Perl, shell ...
Austin, TX · On-site
$134K - $138K/yr
... DFT or clocking.Experience or coursework with digital logic design, RTL, DV (testing), CMOS transistor logics or VLSI concepts.Experience with scripting languages such as TCL, Python, Perl, shell ...
... VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... Work closely with physical design, DFT, and CAD teams to optimize performance, power, and area (PPA ...
... VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... Work closely with physical design, DFT, and CAD teams to optimize performance, power, and area (PPA ...
Dallas, TX · On-site
Working closely with Synthesis, STA, PD and DFT teams to meet all functional requirements ... VLSI design, and Digital Design Architecture • Strong problem-solving and data analysis skills ...
Dallas, TX · On-site
Working closely with Synthesis, STA, PD and DFT teams to meet all functional requirements ... VLSI design, and Digital Design Architecture • Strong problem-solving and data analysis skills ...
Austin, TX · On-site
$134K - $138K/yr
Experience or coursework in one or more of the following areas: physical design, synthesis, DFT or clocking.Experience or coursework with digital logic design, RTL, CMOS transistor logics or VLSI ...
Austin, TX · On-site
$134K - $138K/yr
Experience or coursework in one or more of the following areas: physical design, synthesis, DFT or clocking.Experience or coursework with digital logic design, RTL, CMOS transistor logics or VLSI ...
Austin, TX · On-site
$134K - $138K/yr
Experience or coursework in one or more of the following areas: physical design, synthesis, DFT or clocking. Experience or coursework with digital logic design, RTL, CMOS transistor logics or VLSI ...
Austin, TX · On-site
$134K - $138K/yr
Experience or coursework in one or more of the following areas: physical design, synthesis, DFT or clocking. Experience or coursework with digital logic design, RTL, CMOS transistor logics or VLSI ...
Fort Collins, CO · On-site
$108K - $172K/yr
We are seeking a Senior Digital VLSI Design Engineer with deep expertise in Synthesis, DFT, Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC) sign-off for high speed complex IPs to be ...
Fort Collins, CO · On-site
$108K - $172K/yr
We are seeking a Senior Digital VLSI Design Engineer with deep expertise in Synthesis, DFT, Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC) sign-off for high speed complex IPs to be ...
Williston, VT · On-site +1
$100K - $165K/yr
... VLSI design, software/programming courses). * Experience with Design for Test concepts such as scan, scan compression, MBIST, BSCAN, and macro test development. * Experience with a range of internal ...
Williston, VT · On-site +1
$100K - $165K/yr
... VLSI design, software/programming courses). * Experience with Design for Test concepts such as scan, scan compression, MBIST, BSCAN, and macro test development. * Experience with a range of internal ...
Mountain View, CA · On-site
$100K - $180K/yr
DFT Integration - Work with Design for Test (DFT) teams to ensure scan chain connectivity and testability. Mandatory Skills: VLSI Physical Place and Route. Experience: 8-10 Years. The expected ...
Mountain View, CA · On-site
$100K - $180K/yr
DFT Integration - Work with Design for Test (DFT) teams to ensure scan chain connectivity and testability. Mandatory Skills: VLSI Physical Place and Route. Experience: 8-10 Years. The expected ...
$134K - $138K/yr
Experience or coursework in one or more of the following areas: physical design, synthesis, DFT or clocking. Experience or coursework with digital logic design, RTL, CMOS transistor logics or VLSI ...
$134K - $138K/yr
Experience or coursework in one or more of the following areas: physical design, synthesis, DFT or clocking. Experience or coursework with digital logic design, RTL, CMOS transistor logics or VLSI ...
Austin, TX · On-site
$134K - $138K/yr
Experience or coursework in one or more of the following areas: physical design, synthesis, DFT or clocking.Experience or coursework with digital logic design, RTL, CMOS transistor logics or VLSI ...
Austin, TX · On-site
$134K - $138K/yr
Experience or coursework in one or more of the following areas: physical design, synthesis, DFT or clocking.Experience or coursework with digital logic design, RTL, CMOS transistor logics or VLSI ...
Austin, TX · On-site
$138K - $171K/yr
... constraints, DFT logic and power intent. As a GPU Design Integration Engineer, you will be ... VLSI design.Proficiency in programming techniques and scripting languages (Perl/Ruby/Python)
Austin, TX · On-site
$138K - $171K/yr
... constraints, DFT logic and power intent. As a GPU Design Integration Engineer, you will be ... VLSI design.Proficiency in programming techniques and scripting languages (Perl/Ruby/Python)
Sunnyvale, TX · On-site
$60K - $148K/yr
... DFT) teams to ensure scan chain connectivity and testability. Mandatory Skills: VLSI Board Design. Experience: 5-8 Years. The expected compensation for this role ranges from $60,000 to $148,500
Sunnyvale, TX · On-site
$60K - $148K/yr
... DFT) teams to ensure scan chain connectivity and testability. Mandatory Skills: VLSI Board Design. Experience: 5-8 Years. The expected compensation for this role ranges from $60,000 to $148,500
... in VLSI design, silicon validation, and semiconductor manufacturing flows. What You Can Expect * Assist in implementing DFT structures such as scan chains, boundary scan (JTAG), and Built-In Self ...
... in VLSI design, silicon validation, and semiconductor manufacturing flows. What You Can Expect * Assist in implementing DFT structures such as scan chains, boundary scan (JTAG), and Built-In Self ...
... VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... Understanding of DFT methodologies including Scan and BIST.
... VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... Understanding of DFT methodologies including Scan and BIST.
... VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... Understanding of DFT methodologies including Scan and BIST.
... VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... Understanding of DFT methodologies including Scan and BIST.
Williston, VT · On-site +1
$100K - $165K/yr
... VLSI design, software/programming courses). * Experience with Design for Test concepts such as scan, scan compression, MBIST, BSCAN, and macro test development. * Experience with a range of internal ...
Williston, VT · On-site +1
$100K - $165K/yr
... VLSI design, software/programming courses). * Experience with Design for Test concepts such as scan, scan compression, MBIST, BSCAN, and macro test development. * Experience with a range of internal ...
$138K - $171K/yr
... DFT logic and power intent. Description As a GPU Design Integration Engineer, you will be ... VLSI design. Proficiency in programming techniques and scripting languages (Perl/Ruby/Python)
$138K - $171K/yr
... DFT logic and power intent. Description As a GPU Design Integration Engineer, you will be ... VLSI design. Proficiency in programming techniques and scripting languages (Perl/Ruby/Python)
... VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... Understanding of DFT methodologies including Scan and BIST.
... VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... Understanding of DFT methodologies including Scan and BIST.
This role is ideal for recent graduates or earlycareer engineers interested in VLSI design, silicon validation, and semiconductor manufacturing flows. What You Can Expect * Assist in implementing DFT ...
This role is ideal for recent graduates or earlycareer engineers interested in VLSI design, silicon validation, and semiconductor manufacturing flows. What You Can Expect * Assist in implementing DFT ...
Santa Clara, CA · On-site
$122K - $168K/yr
Understanding of fundamental DFT topics and VLSI areas of power, timing & voltage noise * Experience in Power Analysis, Thermal Analysis & IR Drop tools is a plus. * Experience in application of AI ...
Santa Clara, CA · On-site
$122K - $168K/yr
Understanding of fundamental DFT topics and VLSI areas of power, timing & voltage noise * Experience in Power Analysis, Thermal Analysis & IR Drop tools is a plus. * Experience in application of AI ...
$14.66 - $17.50
1% of jobs
$17.50 - $20.35
3% of jobs
$20.35 - $23.19
7% of jobs
$25.77 is the 25th percentile. Wages below this are outliers.
$23.19 - $26.03
15% of jobs
$26.03 - $28.87
17% of jobs
The median wage is $30.19 / hr.
$28.87 - $31.71
15% of jobs
$34.42 is the 75th percentile. Wages above this are outliers.
$31.71 - $34.55
18% of jobs
$34.55 - $37.39
12% of jobs
$37.39 - $40.23
7% of jobs
$40.23 - $43.07
3% of jobs
$43.07 - $45.91
2% of jobs
$14
$31
$45
A VLSI DFT (Design for Test) job involves designing and implementing testability features in integrated circuits to ensure efficient manufacturing testing and fault detection. Engineers work on techniques like scan chains, built-in self-test (BIST), boundary scan, and automatic test pattern generation (ATPG) to improve chip test coverage and reliability. Their role helps identify manufacturing defects and optimize testing costs while ensuring high-quality silicon.
To thrive as a VLSI DFT (Design-for-Test) engineer, you need a solid background in digital design, test methodologies, and a relevant degree such as Electrical or Electronics Engineering. Proficiency with EDA tools like Synopsys DFT Compiler, Tessent, or Cadence, along with a good understanding of scripting languages and industry-standard protocols, is typically required. Strong problem-solving abilities, attention to detail, and effective communication are vital soft skills in this role. These competencies are crucial for designing efficient, testable chips and collaborating with cross-functional teams to ensure product quality and manufacturability.
VLSI DFT engineers often encounter challenges such as optimizing test coverage without impacting design performance, managing test data volume, and integrating test features into complex chip designs. Staying up-to-date with evolving industry standards and tools, along with strong analytical skills, can help overcome these hurdles. Candidates can best prepare by gaining hands-on experience with leading DFT tools, understanding scan insertion and ATPG methodologies, and collaborating closely with design and verification teams. Emphasizing continuous learning and adaptability will set you up for long-term success in this dynamic and highly technical field.
$134K - $138K/yr
Full-time
Posted 15 days ago
8.1
Based on 661 frontline employees who took The Breakroom Quiz
6th of 30 rated technology retailers
Sourced by ZipRecruiter
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.
Computer and electronic product manufacturing
10,000+ Employees
Cupertino, CA, US
1976
