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From Home Vlsi Dft Jobs (NOW HIRING)

VLSI Design Engineer

Austin, TX · On-site

$134K - $138K/yr

... from scratch. Key Responsibilities for a VLSI Design Engineer: Work closely with Algorithm and ... DFT team: Ensure design is scan-insertable, supports ATPG, BIST, etc. * Backend/Physical design ...

CPU DFT Engineer

Santa Clara, CA · On-site

$142K - $213K/yr

... and digital VLSI designs. Then you'll insure it becomes reality. We're doing a ground up ... at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to ...

DFT Engineer

Mountain View, CA · On-site

$45K - $121K/yr

VLSI Physical Place and Route. Experience: 3-5 Years. The expected compensation for this role ... Applications from veterans and people with disabilities are explicitly welcome. Reinvent your world.

Senior DFT Engineer

Santa Clara, CA

$122K - $168K/yr

Collaborate closely with VLSI and Product Engineering groups to design innovative DFT approaches ... Lead end-to-end planning and timely execution of NVIDIA's new chip bring-up efforts, from pre ...

Senior DFT Engineer

Santa Clara, CA · On-site

$122K - $168K/yr

Collaborate closely with VLSI and Product Engineering groups to design innovative DFT approaches ... Lead end-to-end planning and timely execution of NVIDIA's new chip bring-up efforts, from pre ...

Senior DFT Engineer

Santa Clara, CA · Hybrid

$122K - $168K/yr

... from RTL to verification to post-silicon ATE bring-up. Join a globally recognized team that ... Co-architect novel DFT strategies alongside VLSI and Product Engineering teams to push the ...

Senior DFT Engineer

Santa Clara, CA · On-site

$122K - $168K/yr

... from RTL to verification to post-silicon ATE bring-up. Join a globally recognized team that ... Co-architect novel DFT strategies alongside VLSI and Product Engineering teams to push the ...

... in VLSI CAD, preferably Synthesis, DFT and P&R •     5-10 years of experience with ... at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to ...

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From Home Vlsi Dft information

What is a work-from-home VLSI DFT engineer?

A work-from-home VLSI DFT (Design for Test) engineer is a professional who specializes in designing and implementing test strategies for integrated circuits (ICs) using VLSI (Very-Large-Scale Integration) techniques, while working remotely. Their primary role is to ensure that chips are testable and free of manufacturing defects. They use specialized tools to insert test structures into chip designs, develop test patterns, and collaborate with design and verification teams—all from a remote location. This role requires strong knowledge of digital design, test methodologies, and EDA (Electronic Design Automation) tools.

What are the key skills and qualifications needed to thrive as a work-from-home VLSI DFT engineer?

To thrive as a Work-From-Home VLSI DFT Engineer, you need a solid background in electrical engineering, experience with VLSI design principles, and expertise in DFT methodologies. Proficiency with EDA tools such as Synopsys DFT Compiler, Mentor Tessent, and scripting languages like Python or TCL is typically required. Strong problem-solving skills, attention to detail, and effective remote communication are essential soft skills for excelling in this role. These competencies ensure the successful implementation of testability in chip designs, leading to higher quality products and efficient project collaboration in a remote environment.

What are some common challenges faced by remote VLSI DFT engineers and how can they be addressed?

Remote VLSI Design-for-Test (DFT) engineers often face challenges such as collaborating effectively with cross-functional teams, accessing secure design environments, and staying updated on evolving design tools. To overcome these, companies typically provide secure VPN access, cloud-based EDA tool licenses, and regular virtual meetings to maintain strong communication and project alignment. Proactively reaching out for feedback and participating in online training can also help remote engineers stay connected and up-to-date.

What is the difference between From Home Vlsi Dft vs From Home Vlsi Physical Design?

AspectFrom Home Vlsi DftFrom Home Vlsi Physical Design
Required SkillsDesign for Test (DFT), RTL, EDA tools, scriptingPlacement, routing, synthesis, EDA tools, scripting
Work EnvironmentPrimarily software-based, remote work, design verificationDesign implementation, physical layout, verification
Industry UsageUsed in chip testing and validationUsed in chip layout and fabrication

From Home Vlsi Dft focuses on designing test structures to ensure chip quality, while From Home Vlsi Physical Design involves creating the physical layout of chips. Both roles require EDA tools knowledge and scripting skills, but they serve different stages of chip development. Understanding these differences helps candidates choose the right career path based on their skills and interests.

What cities are hiring for From Home Vlsi Dft jobs?

Cities with the most From Home Vlsi Dft job openings:

What are the most commonly searched types of Vlsi Dft jobs?

The most popular types of Vlsi Dft jobs are:

What states have the most From Home Vlsi Dft jobs?

States with the most job openings for From Home Vlsi Dft jobs include:

Infographic showing various From Home Vlsi Dft job openings in the United States as of June 2026, with employment types broken down into 50% Temporary, and 50% Contract. Highlights an 80% Physical, 1% Hybrid, and 19% Remote job distribution.

VLSI Design Engineer

Retym

Austin, TX • On-site

$134K - $138K/yr

Full-time

Re-posted 3 days ago


Job description

Description
We are looking for talented and experienced VLSI Design Engineers/Micro-architects.
As an VLSI Digital Design Engineer/Micro-architect, you'll have the opportunity to design highly sophisticated, innovative new cutting edge communication systems from scratch.
Key Responsibilities for a VLSI Design Engineer:
Work closely with Algorithm and Architecture teams
  • Understand and translate high-level algorithmic requirements into efficient hardware implementations.

Learn and analyze relevant protocols and standards
  • Interpret protocol specifications (e.g., Ethernet, etc.) and apply them accurately in design.

Participate in all design stages:
  • Micro-architecture definition
  • RTL coding (using Verilog/SystemVerilog)
  • Synthesis-friendly coding and timing-aware design

Collaborate cross-functionally:
  • Verification team: For testbench development, debug support, and functional coverage closure.
  • DFT team: Ensure design is scan-insertable, supports ATPG, BIST, etc.
  • Backend/Physical design team: For floorplanning, timing closure, and routing feedback.

Participate in Design Reviews
  • Present and defend design decisions in peer and formal reviews.

Perform Synthesis and Timing Analysis
  • Generate synthesis constraints (SDC), run synthesis, and analyze timing reports.

Debug and Fix Functional/Timing Issues
  • Collaborate in post-silicon or pre-silicon debug; use waveforms, assertions, and logic analyzers.

Optimize for Area, Power, and Performance (PPA)
  • Identify bottlenecks and opportunities for improvement within RTL.

Documentation
  • Maintain clear design documentation for reusability and reference (e.g., micro-architecture specs, interface docs).

Contribute to IP/SoC Integration
  • Work on integrating design blocks into larger systems and handling system-level interfaces.

Participate in Silicon Bring-up and Validation (optional but valuable)
  • Support bring-up of first silicon and assist with post-silicon validation, if applicable.

Keep up-to-date with Industry Trends and Tools
  • Learn new EDA tools, languages, and methodologies (e.g., CDC, Linting, Formal Verification).

Requirements
Job requirements:
  • +5 years of experience as ASIC/VLSI digital design engineer
  • Strong Verilog/System-Verilog experience
  • Familiar with simulation tools/environments, verification methodologies
  • Strong team player, solid interpersonal skills
  • Entrepreneurial can-do attitude, self-motivated, able to work independently
  • BS/MS in EE/CE from lead universities

Background in one or more of the following domains is an advantage:
  • Familiar with advanced design practices (Clock/Voltage domain crossing, Low Power Design, DFT)
  • Design DSP of oriented blocks
  • Ethernet (100G and above)
  • Scripting experience using several of the following: Python, Perl, TCL