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Physical Design Engineer Internship Jobs (NOW HIRING)

Physical Design Engineer

Santa Clara, CA

$159K - $164K/yr

Physical Design Engineer Location: Santa Clara, CA About the role: We are seeking a seasoned Physical Design Engineer with a strong background in all aspects of Physical Design and Implementation ...

Physical Design Engineer

Cupertino, CA · On-site

$167K - $172K/yr

We have an opportunity for a forward-thinking and unusually hardworking Physical Design Engineer. As a member of our wide-ranging group, you will have the rare and great opportunity to craft upcoming ...

Physical Design Engineer

Beaverton, OR

$141K - $145K/yr

We have an opportunity for a forward-thinking and unusually hardworking Physical Design Engineer. As a member of our wide-ranging group, you will have the rare and great opportunity to craft upcoming ...

Physical Design Engineer

San Francisco, CA · On-site

$160K - $164K/yr

We have an opportunity for a forward-thinking and unusually hardworking Physical Design Engineer. As a member of our wide-ranging group, you will have the rare and great opportunity to craft upcoming ...

Physical Design Engineer

Alameda, CA · Hybrid

$157K - $162K/yr

Physical Design Engineer (PD/PnR) Location: Bay Area / Austin (Hybrid Job Summary Seeking a Physical Design Engineer with strong hands-on experience in block-level and top-level Place & Route using ...

Physical Design Engineer

Hayward, CA · Hybrid

$155K - $160K/yr

Physical Design Engineer (PD/PnR) Location: Bay Area / Austin (Hybrid Job Summary Seeking a Physical Design Engineer with strong hands-on experience in block-level and top-level Place & Route using ...

Physical Design Engineer

Mundelein, IL · Hybrid

$138K - $142K/yr

Physical Design Engineer (PD/PnR) Location: Bay Area / Austin (Hybrid Job Summary Seeking a Physical Design Engineer with strong hands-on experience in block-level and top-level Place & Route using ...

Physical Design Engineer

Sunnyvale, CA · Hybrid

$161K - $166K/yr

Physical Design Engineer (PD/PnR) Location: Bay Area / Austin (Hybrid Job Summary Seeking a Physical Design Engineer with strong hands-on experience in block-level and top-level Place & Route using ...

Physical Design Engineer

Santa Rosa, CA · Hybrid

$148K - $153K/yr

Physical Design Engineer (PD/PnR) Location: Bay Area / Austin (Hybrid Job Summary Seeking a Physical Design Engineer with strong hands-on experience in block-level and top-level Place & Route using ...

Physical Design Engineer

San Mateo, CA · Hybrid

$154K - $159K/yr

Physical Design Engineer (PD/PnR) Location: Bay Area / Austin (Hybrid Job Summary Seeking a Physical Design Engineer with strong hands-on experience in block-level and top-level Place & Route using ...

Physical Design Engineer

Cupertino, CA · On-site

$167K - $172K/yr

We have an opportunity for a forward-thinking and unusually hardworking Physical Design Engineer. As a member of our wide-ranging group, you will have the rare and great opportunity to craft upcoming ...

Physical Design Engineer

San Francisco, CA · Hybrid

$160K - $164K/yr

Physical Design Engineer (PD/PnR) Location: Bay Area / Austin (Hybrid Job Summary Seeking a Physical Design Engineer with strong hands-on experience in block-level and top-level Place & Route using ...

Physical Design Engineer

Santa Clara, CA · Hybrid

$158K - $163K/yr

Physical Design Engineer (PD/PnR) Location: Bay Area / Austin (Hybrid Job Summary Seeking a Physical Design Engineer with strong hands-on experience in block-level and top-level Place & Route using ...

Physical Design Engineer

Cupertino, CA · On-site

$167K - $172K/yr

We have an opportunity for a forward-thinking and unusually hardworking Physical Design Engineer. As a member of our wide-ranging group, you will have the rare and great opportunity to craft upcoming ...

Physical Design Engineer

Beaverton, OR · On-site

$141K - $145K/yr

We have an opportunity for a forward-thinking and unusually hardworking Physical Design Engineer. As a member of our wide-ranging group, you will have the rare and great opportunity to craft upcoming ...

Physical Design Engineer

Fremont, CA · Hybrid

$148K - $153K/yr

Physical Design Engineer (PD/PnR) Location: Bay Area / Austin (Hybrid Job Summary Seeking a Physical Design Engineer with strong hands-on experience in block-level and top-level Place & Route using ...

Physical Design Engineer

San Jose, CA · Hybrid

$159K - $164K/yr

Physical Design Engineer (PD/PnR) Location: Bay Area / Austin (Hybrid Job Summary Seeking a Physical Design Engineer with strong hands-on experience in block-level and top-level Place & Route using ...

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Physical Design Engineer Internship information

See salary details

$95K

$141.5K

How much do physical design engineer internship jobs pay per year?

As of Jun 18, 2026, the average yearly pay for physical design engineer internship in the United States is $139,408.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $140,000.00 per year, depending on experience, location, and employer.

What is the difference between Physical Design Engineer Internship vs Digital IC Design Engineer?

AspectPhysical Design Engineer InternshipDigital IC Design Engineer
Required CredentialsTypically pursuing or recent graduate in Electrical Engineering or Computer EngineeringBachelor's or Master's in Electrical Engineering, Computer Engineering, or related field
Work EnvironmentInternship setting within semiconductor or electronics companies, hands-on design tasksFull-time professional role, involved in digital circuit design and verification
Employer & Industry UsageUsed by semiconductor companies, chip design firms, and tech companies for trainingFull-time employment in similar companies, focusing on digital IC development

The Physical Design Engineer Internship provides hands-on experience in chip layout and physical implementation, often for students or recent grads. In contrast, the Digital IC Design Engineer role involves full-time digital circuit design and verification. Both roles are essential in semiconductor development, but internships serve as entry points for aspiring engineers to gain industry exposure.

How much do VLSI interns get paid?

VLSI internship salaries typically range from $20 to $40 per hour, depending on the company, location, and the intern's experience. Paid internships often include opportunities to work with industry-standard tools and gain practical experience in chip design and verification.

Is a 3.0 GPA good for internships?

For a Physical Design Engineer Internship, a 3.0 GPA is generally considered acceptable, especially if complemented by relevant skills such as knowledge of EDA tools and digital design. While some companies prefer higher GPAs, practical experience, technical skills, and project work can also be important factors in the application process.

What are Physical Design Engineer internships?

Physical Design Engineer internships are opportunities for students or recent graduates to gain hands-on experience in the field of semiconductor design, focusing on the physical implementation of integrated circuits (ICs). Interns typically work alongside experienced engineers to learn about tasks such as floorplanning, placement, routing, timing analysis, and verification using industry-standard Electronic Design Automation (EDA) tools. These internships provide exposure to the complete chip design flow, allowing interns to apply their knowledge of digital design and learn about key challenges in transforming logical circuit designs into manufacturable silicon. The experience is highly valuable for those seeking a career in VLSI or hardware engineering.

What are the key skills and qualifications needed to thrive as a Physical Design Engineer Intern, and why are they important?

To thrive as a Physical Design Engineer Intern, you generally need a solid understanding of digital circuit design, VLSI concepts, and coursework in electrical or computer engineering. Familiarity with EDA tools like Cadence, Synopsys, or Mentor Graphics, along with knowledge of scripting languages such as TCL or Python, is typically required. Strong analytical thinking, attention to detail, and effective communication skills help interns excel in team environments and complex problem-solving. These skills and qualifications are vital for ensuring accurate, efficient chip design and successful integration within engineering teams.

What are the big 4 internships?

The 'Big 4' internships typically refer to internship programs offered by the four largest professional services firms: Deloitte, PricewaterhouseCoopers (PwC), Ernst & Young (EY), and KPMG. These firms offer internships in areas such as consulting, audit, tax, and advisory, providing valuable experience for students pursuing careers in accounting, finance, and consulting. For a Physical Design Engineer Internship, relevant internships might be with semiconductor companies or tech firms, but the 'Big 4' are primarily known for accounting and consulting roles.

What is a physical design internship?

A physical design internship is a temporary position where interns assist in the implementation and optimization of integrated circuit layouts, focusing on tasks such as placement, routing, and timing analysis. Interns typically gain experience with electronic design automation (EDA) tools and work closely with engineering teams to ensure chip performance and manufacturability.

What are some typical projects or tasks a Physical Design Engineer intern can expect to work on during their internship?

As a Physical Design Engineer intern, you’ll typically assist with tasks such as floorplanning, placement, clock tree synthesis, and routing for integrated circuit (IC) designs. You may also help analyze timing, power, and area, supporting senior engineers in optimizing chip layouts. Interns often use industry-standard EDA tools and collaborate closely with teams in RTL design and verification. This hands-on experience allows you to develop your technical skills while gaining insight into the collaborative workflow of semiconductor design.
More about Physical Design Engineer Internship jobs
What cities are hiring for Physical Design Engineer Internship jobs? Cities with the most Physical Design Engineer Internship job openings:
What are the most commonly searched types of Physical Design Engineer jobs? The most popular types of Physical Design Engineer jobs are:
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Physical Design Engineer

Baya Systems

Santa Clara, CA

$159K - $164K/yr

Other

Posted 25 days ago


Job description

Job Title: Physical Design Engineer
 
Location: Santa Clara, CA
 
About the role: We are seeking a seasoned Physical Design Engineer with a strong background in all aspects of Physical Design and Implementation flows. The ideal candidate will play a key role in shaping our technology portfolio, bringing expertise and creativity to our solutions
 
Responsibilities:
 
Own RTL to GDS physical implementation flows for synthesis, floor-planning, place and route, clock tree synthesis, timing & power closure, EM/IR, PDV and final PD sign off
Own physical design & implementation of high-performance designs from block level to system level components
Deep collaboration with Micro-architects to explore performance, power and area trade-offs for high performance and low power designs
Physical implementation feasibility studies and design recommendations for best PPA
Develop methodologies and recipes for various stages of physical implementation
Perform various physical design validation (PDV) flows for Timing, Power, EM/IR, etc. to ensure physical design quality
Perform design rule checking (DRC), (LVS) checks, and other physical verification tasks
Qualifications:
 
BS, MS in Electrical Engineering or Computer Engineering or related degree
Experience in all aspects of physical design including synthesis, floor planning, place & route, timing & power closure, EM/IR, physical design validation, etc
Experience with synthesis, place & route, static timing analysis and PDV tools
Experience in implementing clock trees and power grids
Experience with scripting for physical design flow automation
Experience with Synopsys Design Compiler, Prime Time, ICC, Fusion Compiler etc.
Good knowledge of high-performance and low-power microarchitecture and logic design principles
Understanding of modern (sub 7nm) sub-micron technology nodes and device physics
Basic knowledge of System/SoC Architecture and System Verilog RTL coding
Strong communication and collaboration skills