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Physical Design Engineer Internship Jobs in Seattle, WA

Mundi

Principal ASIC Physical Design Engineer

Seattle, WA · On-site

$190 - $280/hr

The Role We are looking for a Principal ASIC Physical Design Engineer to lead the implementation of complex SoCs for next‑generation satellite and space systems. You will own the full physical ...

K2 Space

Senior ASIC Physical Design Engineer

Seattle, WA · On-site

$170K - $250K/yr

The Role We are seeking a Senior ASIC Physical Design Engineer to help implement advanced SoCs that power next-generation satellite and space systems. In this role, you will contribute to the full ...

K2 Space

Senior ASIC Physical Design Engineer

Seattle, WA · On-site

$170K - $250K/yr

The Role We are seeking a Senior ASIC Physical Design Engineer to help implement advanced SoCs that power next-generation satellite and space systems. In this role, you will contribute to the full ...

K2 Space

Senior ASIC Physical Design Engineer

Seattle, WA · On-site

$170K - $250K/yr

The Role We are seeking a Senior ASIC Physical Design Engineer to help implement advanced SoCs that power next-generation satellite and space systems. In this role, you will contribute to the full ...

Amazon

Sr. Mechanical Design Engineer

Redmond, WA · On-site

$100K - $138K/yr

The Sr. Mechanical Design Engineer will be a member of the Amazon Leo Inter-Satellite Link team ... physical design, while optimizing to support high volume production and meeting cross discipline ...

Amazon

Sr. Mechanical Design Engineer

Redmond, WA · On-site

$100K - $138K/yr

The Sr. Mechanical Design Engineer will be a member of the Amazon Leo Inter-Satellite Link team ... physical design, while optimizing to support high volume production and meeting cross discipline ...

Ashby

Design Engineer - Americas

Seattle, WA · Remote

$126K - $250K/yr

You have 2+ years of continuous experience (e.g., internships don't count) as an Engineer or a Designer. You have good proficiency in both Design and Engineering, with exceptional proficiency in the ...

Amazon

Sr. Mechanical Design Engineer

Redmond, WA · On-site

$100K - $138K/yr

The Sr. Mechanical Design Engineer will be a member of the Amazon Leo Inter-Satellite Link team ... physical design, while optimizing to support high volume production and meeting cross discipline ...

ATS Companies

Design Engineer

Renton, WA · On-site

$68K - $124K/yr

The Design Engineer is a key member of the Engineering Services Group, a centralized team focused ... Strong troubleshooting and problem-solving abilities WORK ENVIRONMENT AND PHYSICAL DEMANDS: This ...

ATS Automation

Design Engineer

Renton, WA · On-site

$68K - $124K/yr

The Design Engineer is a key member of the Engineering Services Group, a centralized team focused ... Strong troubleshooting and problem-solving abilities WORK ENVIRONMENT AND PHYSICAL DEMANDS: This ...

ATS Companies

Design Engineer

Renton, WA · On-site

$68K - $124K/yr

The Design Engineer is a key member of the Engineering Services Group, a centralized team focused ... Strong troubleshooting and problem-solving abilities WORK ENVIRONMENT AND PHYSICAL DEMANDS: This ...

amphenol

Design Engineer

Seattle, WA · Hybrid

SUMMARY We are seeking an experienced engineer to join our team and contribute to the design and ... Work is performed in a normal office environment with minimal physical risks involved. The noise ...

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All JobsPhysical Design Engineer JobsPhysical Design Engineer Internship JobsPhysical Design Engineer Internship Jobs in Seattle, WA

Physical Design Engineer Internship information

See Seattle, WA salary details

$108.1K

$161K

How much do physical design engineer internship jobs pay per year?

As of Aug 13, 2026, the average yearly pay for physical design engineer internship in Seattle, WA is $158,651.00, according to ZipRecruiter salary data. Most workers in this role earn between $154,800.00 and $159,300.00 per year, depending on experience, location, and employer.

What is the difference between Physical Design Engineer Internship vs Digital IC Design Engineer?

AspectPhysical Design Engineer InternshipDigital IC Design Engineer
Required CredentialsTypically pursuing or recent graduate in Electrical Engineering or Computer EngineeringBachelor's or Master's in Electrical Engineering, Computer Engineering, or related field
Work EnvironmentInternship setting within semiconductor or electronics companies, hands-on design tasksFull-time professional role, involved in digital circuit design and verification
Employer & Industry UsageUsed by semiconductor companies, chip design firms, and tech companies for trainingFull-time employment in similar companies, focusing on digital IC development

The Physical Design Engineer Internship provides hands-on experience in chip layout and physical implementation, often for students or recent grads. In contrast, the Digital IC Design Engineer role involves full-time digital circuit design and verification. Both roles are essential in semiconductor development, but internships serve as entry points for aspiring engineers to gain industry exposure.

What is a physical design engineer internship?

Physical Design Engineer internships are opportunities for students or recent graduates to gain hands-on experience in the field of semiconductor design, focusing on the physical implementation of integrated circuits (ICs). Interns typically work alongside experienced engineers to learn about tasks such as floorplanning, placement, routing, timing analysis, and verification using industry-standard Electronic Design Automation (EDA) tools. These internships provide exposure to the complete chip design flow, allowing interns to apply their knowledge of digital design and learn about key challenges in transforming logical circuit designs into manufacturable silicon. The experience is highly valuable for those seeking a career in VLSI or hardware engineering.

What are the key skills and qualifications needed to thrive as a physical design engineer intern?

To thrive as a Physical Design Engineer Intern, you generally need a solid understanding of digital circuit design, VLSI concepts, and coursework in electrical or computer engineering. Familiarity with EDA tools like Cadence, Synopsys, or Mentor Graphics, along with knowledge of scripting languages such as TCL or Python, is typically required. Strong analytical thinking, attention to detail, and effective communication skills help interns excel in team environments and complex problem-solving. These skills and qualifications are vital for ensuring accurate, efficient chip design and successful integration within engineering teams.

What do physical design engineer interns do?

As a Physical Design Engineer intern, you’ll typically assist with tasks such as floorplanning, placement, clock tree synthesis, and routing for integrated circuit (IC) designs. You may also help analyze timing, power, and area, supporting senior engineers in optimizing chip layouts. Interns often use industry-standard EDA tools and collaborate closely with teams in RTL design and verification. This hands-on experience allows you to develop your technical skills while gaining insight into the collaborative workflow of semiconductor design.
What are the most commonly searched types of Physical Design Engineer jobs in Seattle, WA? The most popular types of Physical Design Engineer jobs in Seattle, WA are:
What are popular job titles related to Physical Design Engineer Internship jobs in Seattle, WA? For Physical Design Engineer Internship jobs in Seattle, WA, the most frequently searched job titles are:
What job categories do people searching Physical Design Engineer Internship jobs in Seattle, WA look for? The top searched job categories for Physical Design Engineer Internship jobs in Seattle, WA are:
What cities near Seattle, WA are hiring for Physical Design Engineer Internship jobs? Cities near Seattle, WA with the most Physical Design Engineer Internship job openings:
Physical Design Engineer Internship jobs near you
Infographic showing various Physical Design Engineer Internship job openings in Seattle, WA as of July 2026, with employment types broken down into 10% Internship, 80% Full Time, and 10% Contract. Highlights an 100% In-person job distribution, with an average salary of $158,651 per year, or $76.3 per hour.

Principal ASIC Physical Design Engineer

K2 Space

Seattle, WA

$190K - $280K/yr

Full-time

Medical, Dental, Vision, Life, PTO

Re-posted 13 days ago

Job description

The Role

We are looking for a Principal ASIC Physical Design Engineer to lead the implementation of complex SoCs for next-generation satellite and space systems. You will own the full physical design flow-from RTL handoff to GDSII-and collaborate closely with architecture, RTL design, DFT, and packaging teams. This role also involves managing external physical design partners, driving tool and flow decisions, and ensuring first-pass silicon success in advanced FinFET technologies. You'll be a key contributor in achieving timing closure, optimizing PPA, and supporting design integration with external partners. You will be part of a collaborative design team developing state-of-the-art mixed-signal SoCs to be hosted on some of the largest, most powerful, rapidly designed and rapidly manufactured satellites ever deployed in space. In your first 6 months, you will develop and implement new SoC sub-systems for satellite communications and beyond. In your first two years, you will have contributed to developing cutting-edge SoCs that will fly in space. 

Responsibilities

  • Own the complete RTL-to-GDSII flow: synthesis, floorplanning, place & route, clock tree synthesis (CTS), static timing analysis (STA), physical verification (DRC/LVS), and sign-off.
  • Develop and maintain physical design methodologies, scripts, and automation to optimize performance, power, and area (PPA).
  • Collaborate with front-end and verification teams to ensure clean handoffs, timing closure, and efficient design iteration.
  • Drive timing closure across multiple voltage and process corners, including sign-off with foundry-qualified tools.
  • Partner with package, SI/PI, and test teams for package-aware floorplanning and chip-to-board integration.
  • Manage and technically guide external physical design partners and service vendors, ensuring alignment on milestones, deliverables, and quality standards.
  • Work with EDA vendors to debug and optimize tool flows, and evaluate new methodologies.
  • Support chip bring-up and debug through close collaboration with post-silicon and test teams.
  • Support your product through production and spaceflight.

Required Qualifications 

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
  • 10+ years of experience in ASIC physical design for high-performance SoCs.
  • Proven end-to-end expertise in RTL-to-GDSII flows using industry tools (Synopsys, Cadence, or Siemens).
  • Strong hands-on experience with timing closure, IR drop analysis, and ECO implementation.
  • Deep understanding of physical design constraints for multi-clock, multi-voltage, and hierarchical SoCs.
  • Experience with advanced FinFET process nodes.
  • Prior experience managing or coordinating offshore/outsourced PD teams or vendors.
  • Familiarity with DFT integration, STA sign-off, and power domain implementation (UPF/CPF).
  • Excellent communication, leadership, and cross-functional collaboration skills.
  • Act as technical leader and subject-matter expert helping to teach, grow, and mentor others in the team.

Preferred Qualifications 

  • Exposure to radiation-hardened or space-qualified ASICs.
  • Experience with chip-package co-design or advanced packaging (2.5D/3D).
  • Familiarity with physical design service vendor management or offshore collaboration.
  • Experience driving tapeouts through TSMC.
  • Experience with Gate-All-Around technologies.
  • Experience working in cross-functional, geographically distributed teams.

Compensation and Benefits:

  • Base salary range for this role is $190,000 - $280,000 + equity in the company
  • Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
  • Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks
K2 Space logo

About K2 Space

Sourced by ZipRecruiter

Industry

Guided missile and space vehicle manufacturing

Company size

11 - 50 Employees

Headquarters location

Los Angeles, CA, US

Year founded

2022

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