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Physical Design Engineer Internship Jobs in Toronto, ON

Amd

Senior Physical Design Engineer

Thornhill, ON · Hybrid

As a seasoned Physical Design engineer, you will be working with a diverse team of physical design engineers, RTL design engineers, and managers from NBIO IP team. You will drive physical ...

Amd

IREM Physical Design Engineer

Thornhill, ON · Hybrid

You'll partner closely with physical design, packaging, and CAD teams, gaining exposure to advanced ... Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field ...

Qualcomm

Physical Design Engineer, Staff

Toronto, ON · On-site

$124 - $174/hr

What You'll Need * 7+ years of Physical Design experience * Bachelor's degree in Electrical or Computer Engineering or equivalent * Low-Power Designs experience desired * SOC design experience is ...

Net2Source (N2S)

Senior Design Engineer

Markham, ON · Hybrid

CA$75 - CA$80/hr

Work with synthesis and backend teams for physical implementation. * RTL Design Engineer to help with some IP work * Need experience with some AI tools, how to use AI tools to speed up the ...

Amd

RTL Design Engineer

Thornhill, ON · Hybrid

An RTL Design Engineering role in our Security IP (SECIP) team, where a large number of individual ... mental or physical disability, national origin, race, religion, political and/or third-party ...

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Physical Design Engineer Internship information

What is a physical design engineer internship?

Physical Design Engineer internships are opportunities for students or recent graduates to gain hands-on experience in the field of semiconductor design, focusing on the physical implementation of integrated circuits (ICs). Interns typically work alongside experienced engineers to learn about tasks such as floorplanning, placement, routing, timing analysis, and verification using industry-standard Electronic Design Automation (EDA) tools. These internships provide exposure to the complete chip design flow, allowing interns to apply their knowledge of digital design and learn about key challenges in transforming logical circuit designs into manufacturable silicon. The experience is highly valuable for those seeking a career in VLSI or hardware engineering.

What do physical design engineer interns do?

As a Physical Design Engineer intern, you’ll typically assist with tasks such as floorplanning, placement, clock tree synthesis, and routing for integrated circuit (IC) designs. You may also help analyze timing, power, and area, supporting senior engineers in optimizing chip layouts. Interns often use industry-standard EDA tools and collaborate closely with teams in RTL design and verification. This hands-on experience allows you to develop your technical skills while gaining insight into the collaborative workflow of semiconductor design.

What are the key skills and qualifications needed to thrive as a physical design engineer intern?

To thrive as a Physical Design Engineer Intern, you generally need a solid understanding of digital circuit design, VLSI concepts, and coursework in electrical or computer engineering. Familiarity with EDA tools like Cadence, Synopsys, or Mentor Graphics, along with knowledge of scripting languages such as TCL or Python, is typically required. Strong analytical thinking, attention to detail, and effective communication skills help interns excel in team environments and complex problem-solving. These skills and qualifications are vital for ensuring accurate, efficient chip design and successful integration within engineering teams.

What is the difference between Physical Design Engineer Internship vs Digital IC Design Engineer?

AspectPhysical Design Engineer InternshipDigital IC Design Engineer
Required CredentialsTypically pursuing or recent graduate in Electrical Engineering or Computer EngineeringBachelor's or Master's in Electrical Engineering, Computer Engineering, or related field
Work EnvironmentInternship setting within semiconductor or electronics companies, hands-on design tasksFull-time professional role, involved in digital circuit design and verification
Employer & Industry UsageUsed by semiconductor companies, chip design firms, and tech companies for trainingFull-time employment in similar companies, focusing on digital IC development

The Physical Design Engineer Internship provides hands-on experience in chip layout and physical implementation, often for students or recent grads. In contrast, the Digital IC Design Engineer role involves full-time digital circuit design and verification. Both roles are essential in semiconductor development, but internships serve as entry points for aspiring engineers to gain industry exposure.

What are the most commonly searched types of Physical Design Engineer jobs in Toronto, ON?

The most popular types of Physical Design Engineer jobs in Toronto, ON are:

What are popular job titles related to Physical Design Engineer Internship jobs in Toronto, ON?

For Physical Design Engineer Internship jobs in Toronto, ON, the most frequently searched job titles are:

What job categories do people searching Physical Design Engineer Internship jobs in Toronto, ON look for?

The top searched job categories for Physical Design Engineer Internship jobs in Toronto, ON are:

Physical Design Engineer Internship jobs near you
Infographic showing various Physical Design Engineer Internship job openings in Toronto, ON as of July 2026, with employment types broken down into 100% Full Time. Highlights an 100% In-person job distribution.

Manager, Physical Design Engineer

Astera Labs

Toronto, ON • On-site

Full-time

Re-posted 23 days ago

Job description

Role Overview

Astera Labs is seeking a Physical Design Engineering Manager to lead a team of physical design engineers at our Toronto site, driving the implementation of connectivity ASICs within our Signal Connectivity Group. This group is responsible for products that enable high-speed serial connectivity including PCIe retimers, Ethernet retimers, and signal conditioning solutions deployed across the world's largest AI clusters and hyperscale data centers.

As an Physical Design Manager Engineering Manager, you will combine hands-on technical leadership with people management, owning physical design execution from RTL to GDSII while building and mentoring a high-performing team. You will drive floorplanning, place-and-route, timing closure, and sign-off for complex designs requiring deep understanding of high-speed physical layer interfaces and SerDes integration at TSMC advanced nodes. This role is fully on-site at our Toronto location.

Basic Qualifications

  • Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field; Master's preferred.
  • 10+ years of experience in physical design implementation of complex SoCs at advanced nodes (7nm and below).
  • 2+ years of experience leading teams or projects with demonstrated ability to mentor and develop engineers.
  • Hands-on expertise across the physical design flow: synthesis, place-and-route, CTS, extraction, timing closure, EM-IR, DRC/LVS, and equivalence checking.
  • Proficiency with Cadence Innovus and/or Synopsys Fusion Compiler/ICC2 and supporting toolchains.
  • Strong scripting ability in Tcl, Python, and/or Perl.
  • Professional attitude with the ability to prioritize a dynamic list of tasks, plan and prepare for customer meetings in advance, and work with minimal guidance.
  • Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind! 

Required Experience

  • Build, lead, and mentor a physical design team, owning Physical Design execution and team development for Signal Connectivity Group products.
  • Drive block and top-level physical design implementation from floorplan through tapeout for retimer and signal conditioning ASICs.
  • Collaborate with RTL, DFT, STA, EMIR, and verification teams to drive design convergence from synthesis through sign-off.
  • Work with IP vendors for both RTL and hard-macro integration, ensuring placement constraints and routing guidelines are met.
  • Drive team execution, hiring, career development, and sprint planning for the Toronto PD team.
  • Establish physical design best practices, flow improvements, and quality checks to scale execution across multiple concurrent programs.
  • Coordinate with global PD teams (San Jose, Irvine, Bangalore) to ensure consistent methodology and design quality.
  • Experience with Cadence and/or Synopsys physical design tools/flows.

Preferred Experience/Nice to Have

  • Deep understanding of high-speed SerDes physical layer, including equalization, CDR, and signal integrity considerations impacting physical design.
  • Knowledge of physical layer timing challenges specific to high-speed serial interfaces.
  • Track record of building and scaling physical design teams through multiple tapeouts.
  • Knowledge of agentic AI solutions for EDA automation.

Base salary range is CAD 180,000 to CAD 220,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives, and benefits.

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