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Physical Design Engineer Intern Jobs in Toronto, ON

Amd

Senior Physical Design Engineer

Thornhill, ON · Hybrid

As a seasoned Physical Design engineer, you will be working with a diverse team of physical design engineers, RTL design engineers, and managers from NBIO IP team. You will drive physical ...

Qualcomm

Physical Design Engineer, Staff

Toronto, ON · On-site

$124 - $174/hr

What You'll Need * 7+ years of Physical Design experience * Bachelor's degree in Electrical or Computer Engineering or equivalent * Low-Power Designs experience desired * SOC design experience is ...

Amd

IREM Physical Design Engineer

Thornhill, ON · Hybrid

You'll partner closely with physical design, packaging, and CAD teams, gaining exposure to advanced ... Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field ...

CRB

Mechanical Engineer Intern - Fall

Toronto, ON

From oncology and rare disorders to COVID-19 or alternative proteins, our design and construction ... We are actively seeking a Mechanical Engineer Intern to join CRB. Join our firm for an internship ...

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Physical Design Engineer Intern information

What does a physical design engineer intern do?

A Physical Design Engineer Intern assists in the process of transforming a circuit design (RTL) into a real, manufacturable layout for semiconductor chips. They work on tasks such as floorplanning, placement, routing, timing analysis, and verifying that the chip design meets all physical and electrical requirements. Interns typically use electronic design automation (EDA) tools to perform these tasks and collaborate with experienced engineers. Their work is crucial in ensuring that chips are both functional and manufacturable at scale.

What skills and qualifications are needed to thrive as a physical design engineer intern?

To thrive as a Physical Design Engineer Intern, you generally need a solid background in electrical engineering, digital circuit design, and semiconductor fundamentals, often supported by ongoing university studies in a related field. Familiarity with industry-standard EDA tools such as Cadence, Synopsys, or Mentor Graphics, as well as scripting languages like TCL or Python, is highly valuable. Attention to detail, problem-solving abilities, and effective teamwork are crucial soft skills for excelling in this role. These skills and qualifications are important because they ensure accurate chip layouts, efficient workflows, and successful collaboration within complex engineering teams.

What types of projects and tasks can a physical design engineer intern expect to work on during their internship?

As a Physical Design Engineer Intern, you will typically be involved in supporting the design and verification of integrated circuits at the physical level. Common tasks include assisting with floorplanning, placement and routing, timing analysis, and running design rule checks using industry-standard EDA tools. You may also participate in team meetings, collaborate with senior engineers, and help resolve issues related to power, performance, and area optimization. These hands-on experiences are designed to help you build practical skills and gain a deeper understanding of the physical design flow in VLSI chip development.

What is the difference between Physical Design Engineer Intern vs Digital Design Engineer Intern?

AspectPhysical Design Engineer InternDigital Design Engineer Intern
Required CredentialsTypically pursuing or holding a degree in Electrical Engineering or Computer EngineeringTypically pursuing or holding a degree in Electrical Engineering or Computer Engineering
Work EnvironmentDesigning and implementing physical chip layouts, working with EDA toolsDesigning digital logic circuits, working on HDL coding and simulation
Industry UsageFoundries, semiconductor companies, integrated circuit design firmsSemiconductor companies, integrated circuit design firms, tech companies

Physical Design Engineer Interns focus on translating digital logic designs into physical layouts for chips, working closely with EDA tools. Digital Design Engineer Interns concentrate on creating and simulating digital logic circuits using hardware description languages. Both roles are essential in chip development but differ in their specific tasks and focus areas.

What are the most commonly searched types of Physical Design Engineer jobs in Toronto, ON?

The most popular types of Physical Design Engineer jobs in Toronto, ON are:

What are popular job titles related to Physical Design Engineer Intern jobs in Toronto, ON?

For Physical Design Engineer Intern jobs in Toronto, ON, the most frequently searched job titles are:

What job categories do people searching Physical Design Engineer Intern jobs in Toronto, ON look for?

The top searched job categories for Physical Design Engineer Intern jobs in Toronto, ON are:

What cities near Toronto, ON are hiring for Physical Design Engineer Intern jobs?

Cities near Toronto, ON with the most Physical Design Engineer Intern job openings:

Physical Design Engineer Intern jobs near you
Infographic showing various Physical Design Engineer Intern job openings in Toronto, ON as of August 2026, with employment types broken down into 1% As Needed, 79% Full Time, 16% Part Time, 3% Contract, and 1% Nights. Highlights an 93% Physical, 4% Hybrid, and 3% Remote job distribution.

Manager, Physical Design Engineer

Toronto, ON • On-site

Astera Labs
Semiconductor and Electronic Component Manufacturing • 11 - 50 employees
Learn more about Astera Labsexternal

Full-time

Re-posted 23 days ago

Job description

Role Overview

Astera Labs is seeking a Physical Design Engineering Manager to lead a team of physical design engineers at our Toronto site, driving the implementation of connectivity ASICs within our Signal Connectivity Group. This group is responsible for products that enable high-speed serial connectivity including PCIe retimers, Ethernet retimers, and signal conditioning solutions deployed across the world's largest AI clusters and hyperscale data centers.

As an Physical Design Manager Engineering Manager, you will combine hands-on technical leadership with people management, owning physical design execution from RTL to GDSII while building and mentoring a high-performing team. You will drive floorplanning, place-and-route, timing closure, and sign-off for complex designs requiring deep understanding of high-speed physical layer interfaces and SerDes integration at TSMC advanced nodes. This role is fully on-site at our Toronto location.

Basic Qualifications

  • Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field; Master's preferred.
  • 10+ years of experience in physical design implementation of complex SoCs at advanced nodes (7nm and below).
  • 2+ years of experience leading teams or projects with demonstrated ability to mentor and develop engineers.
  • Hands-on expertise across the physical design flow: synthesis, place-and-route, CTS, extraction, timing closure, EM-IR, DRC/LVS, and equivalence checking.
  • Proficiency with Cadence Innovus and/or Synopsys Fusion Compiler/ICC2 and supporting toolchains.
  • Strong scripting ability in Tcl, Python, and/or Perl.
  • Professional attitude with the ability to prioritize a dynamic list of tasks, plan and prepare for customer meetings in advance, and work with minimal guidance.
  • Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind! 

Required Experience

  • Build, lead, and mentor a physical design team, owning Physical Design execution and team development for Signal Connectivity Group products.
  • Drive block and top-level physical design implementation from floorplan through tapeout for retimer and signal conditioning ASICs.
  • Collaborate with RTL, DFT, STA, EMIR, and verification teams to drive design convergence from synthesis through sign-off.
  • Work with IP vendors for both RTL and hard-macro integration, ensuring placement constraints and routing guidelines are met.
  • Drive team execution, hiring, career development, and sprint planning for the Toronto PD team.
  • Establish physical design best practices, flow improvements, and quality checks to scale execution across multiple concurrent programs.
  • Coordinate with global PD teams (San Jose, Irvine, Bangalore) to ensure consistent methodology and design quality.
  • Experience with Cadence and/or Synopsys physical design tools/flows.

Preferred Experience/Nice to Have

  • Deep understanding of high-speed SerDes physical layer, including equalization, CDR, and signal integrity considerations impacting physical design.
  • Knowledge of physical layer timing challenges specific to high-speed serial interfaces.
  • Track record of building and scaling physical design teams through multiple tapeouts.
  • Knowledge of agentic AI solutions for EDA automation.

Base salary range is CAD 180,000 to CAD 220,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives, and benefits.

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