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Physical Design Engineer Internship Jobs (NOW HIRING)

Etched

Physical Design Engineer

Cupertino, CA

$2.0K/mo

Physical Design Engineer Etched is looking for exceptional PD engineers to join our team. The candidate will be responsible for working with 3rd party design services to implement and verify physical ...

Apple

Physical Design Engineer

Cupertino, CA

$126K - $220K/yr

Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII. Your responsibilities include ...

Apple

Physical Design Engineer

Bodega Bay, CA

$147K - $272K/yr

Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII. Your responsibilities include ...

Apple

Physical Design Engineer

Bodega Bay, CA

$257K - $386K/yr

Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII. Your responsibilities include ...

Apple

Physical Design Engineer

Cupertino, CA · On-site

$126K - $190K/yr

Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII. Your responsibilities include ...

Wipro Limited

Physical Design Engineer

Mountain View, CA · On-site

$100K - $180K/yr

Physical Design Engineer City: Mountain View State/Province: California Posting Start Date: 5/12/26 Wipro Limited (NYSE: WIT, BSE: 507685, NSE: WIPRO) is a leading technology services and consulting ...

CivicMinds, Inc.

Physical Design Engineer

San Diego, CA · On-site

$145K - $150K/yr

Physical design engineers are ideally creative, motivated, energetic, pleasant to work with, and put the needs of the team first. These candidates will be responsible for designs and test structures ...

The PJF Group

Physical Design Engineer

Bodega Bay, CA · On-site

$161K - $166K/yr

We're looking for a hands-on Physical Design Engineer to support complex SoC projects for our client who designs and delivers advanced System-on-Chip solutions across multiple emerging technologies.

Ayar Labs

Engineer, Physical Design

San Jose, CA · On-site

$120K - $160K/yr

Prior internship or co-op experience in a Physical Design or Hardware Engineering role. * Familiarity with physical verification tools such as Mentor Calibre or Synopsys IC Validator. * Understanding ...

Ayar Labs

Engineer, Physical Design

San Jose, CA · On-site

$120K - $160K/yr

Prior internship or co-op experience in a Physical Design or Hardware Engineering role. * Familiarity with physical verification tools such as Mentor Calibre or Synopsys IC Validator. * Understanding ...

The PJF Group

Physical Design Engineer

Bodega Bay, CA · On-site

$180K - $230K/yr

We're looking for a hands-on Physical Design Engineer to support complex SoC projects for our client who designs and delivers advanced System-on-Chip solutions across multiple emerging technologies.

Talent 101, Inc.

Physical Design Engineer

Frisco, TX · On-site

$127K - $131K/yr

This is a full time position with our company doing Physical Design Engineering. What you'll do * Lead end to end Physical Design from floorplan to GDS * Own full PnR flow: placement, CTS, routing ...

Mirafra Technology

Physical Design Engineer

San Diego, CA

$144K - $148K/yr

Job Overview: The Graphics team is looking for Experienced Physical Design Engineers to work on Adreno Graphics cores in the area of Physical Implementation. Responsibilities: The Physical ...

Wipro Limited

Physical Design Engineer

Sunnyvale, TX · On-site

$60K - $148K/yr

Physical Design Engineer City: Sunnyvale State/Province: California Posting Start Date: 5/28/26 Wipro Limited (NYSE: WIT, BSE: 507685, NSE: WIPRO) is a leading technology services and consulting ...

TSMC

Physical Design Engineer (7452)

San Jose, CA · On-site

$155K - $160K/yr

This is an exciting opportunity for an engineer with a strong foundation in VLSI design, a passion ... Prior internship or professional experience in physical design, circuit design, or related ...

Google

Physical Design Engineer

Sunnyvale, CA · On-site

$159K - $164K/yr

As a Physical Design Engineer, you will collaborate closely with cross-functional design, Design for Testing (DFT), architecture, power, and packaging engineers. In this role, you will address ...

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Physical Design Engineer Internship information

See salary details

$95K

$141.5K

How much do physical design engineer internship jobs pay per year?

As of Jun 18, 2026, the average yearly pay for physical design engineer internship in the United States is $139,408.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $140,000.00 per year, depending on experience, location, and employer.

What is the difference between Physical Design Engineer Internship vs Digital IC Design Engineer?

AspectPhysical Design Engineer InternshipDigital IC Design Engineer
Required CredentialsTypically pursuing or recent graduate in Electrical Engineering or Computer EngineeringBachelor's or Master's in Electrical Engineering, Computer Engineering, or related field
Work EnvironmentInternship setting within semiconductor or electronics companies, hands-on design tasksFull-time professional role, involved in digital circuit design and verification
Employer & Industry UsageUsed by semiconductor companies, chip design firms, and tech companies for trainingFull-time employment in similar companies, focusing on digital IC development

The Physical Design Engineer Internship provides hands-on experience in chip layout and physical implementation, often for students or recent grads. In contrast, the Digital IC Design Engineer role involves full-time digital circuit design and verification. Both roles are essential in semiconductor development, but internships serve as entry points for aspiring engineers to gain industry exposure.

How much do VLSI interns get paid?

VLSI internship salaries typically range from $20 to $40 per hour, depending on the company, location, and the intern's experience. Paid internships often include opportunities to work with industry-standard tools and gain practical experience in chip design and verification.

Is a 3.0 GPA good for internships?

For a Physical Design Engineer Internship, a 3.0 GPA is generally considered acceptable, especially if complemented by relevant skills such as knowledge of EDA tools and digital design. While some companies prefer higher GPAs, practical experience, technical skills, and project work can also be important factors in the application process.

What are Physical Design Engineer internships?

Physical Design Engineer internships are opportunities for students or recent graduates to gain hands-on experience in the field of semiconductor design, focusing on the physical implementation of integrated circuits (ICs). Interns typically work alongside experienced engineers to learn about tasks such as floorplanning, placement, routing, timing analysis, and verification using industry-standard Electronic Design Automation (EDA) tools. These internships provide exposure to the complete chip design flow, allowing interns to apply their knowledge of digital design and learn about key challenges in transforming logical circuit designs into manufacturable silicon. The experience is highly valuable for those seeking a career in VLSI or hardware engineering.

What are the key skills and qualifications needed to thrive as a Physical Design Engineer Intern, and why are they important?

To thrive as a Physical Design Engineer Intern, you generally need a solid understanding of digital circuit design, VLSI concepts, and coursework in electrical or computer engineering. Familiarity with EDA tools like Cadence, Synopsys, or Mentor Graphics, along with knowledge of scripting languages such as TCL or Python, is typically required. Strong analytical thinking, attention to detail, and effective communication skills help interns excel in team environments and complex problem-solving. These skills and qualifications are vital for ensuring accurate, efficient chip design and successful integration within engineering teams.

What are the big 4 internships?

The 'Big 4' internships typically refer to internship programs offered by the four largest professional services firms: Deloitte, PricewaterhouseCoopers (PwC), Ernst & Young (EY), and KPMG. These firms offer internships in areas such as consulting, audit, tax, and advisory, providing valuable experience for students pursuing careers in accounting, finance, and consulting. For a Physical Design Engineer Internship, relevant internships might be with semiconductor companies or tech firms, but the 'Big 4' are primarily known for accounting and consulting roles.

What is a physical design internship?

A physical design internship is a temporary position where interns assist in the implementation and optimization of integrated circuit layouts, focusing on tasks such as placement, routing, and timing analysis. Interns typically gain experience with electronic design automation (EDA) tools and work closely with engineering teams to ensure chip performance and manufacturability.

What are some typical projects or tasks a Physical Design Engineer intern can expect to work on during their internship?

As a Physical Design Engineer intern, you’ll typically assist with tasks such as floorplanning, placement, clock tree synthesis, and routing for integrated circuit (IC) designs. You may also help analyze timing, power, and area, supporting senior engineers in optimizing chip layouts. Interns often use industry-standard EDA tools and collaborate closely with teams in RTL design and verification. This hands-on experience allows you to develop your technical skills while gaining insight into the collaborative workflow of semiconductor design.
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Physical Design Engineer Internship jobs near you

Physical Design Engineer

Etched

Cupertino, CA

$2.0K/mo

Other

Medical, Dental, Vision

Posted 24 days ago

Job description

About Etched

Etched is building AI chips that are hard-coded for individual model architectures. Our first product (Sohu) only supports transformers, but has an order of magnitude more throughput and lower latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep chain-of-thought reasoning.

Physical Design Engineer 

Etched is looking for exceptional PD engineers to join our team. The candidate will be responsible for working with 3rd party design services to implement and verify physical designs, and will help Etched as we work to improve iteration speed on physical design.

Representative projects:

  • Supervise the outsourcing of physical design to a 3rd party service
  • Deeply understand what is involved in physical design
  • Running Physical Design flows to close blocks, support ASIC infrastructure, automate Physical Design flows, improve CAD infrastructure
  • Drive dashboards that show the convergence of projects related to Physical Design
  • Optimize tool flows, working with EDA vendors to incorporate the latest features
  • Accountable for block level closure

Requirements:

  • 2+ years of previous experience with PD
  • Tools, flow, and design methodology from RTL synthesis to GDSII sign-off
  • Experience with back-end design and timing closure on 3nm-7nm
  • Experience with UPF-based low power design methodology, power verification, synthesis, scan insertion/ATPG, formal verification, floorplanning, placement, CTS, routing, IR drop, and EM/antenna analysis
  • Deeply creative and able to think from first principles

Desired qualifications:

  • Familiarity with transformer models and machine learning.
  • Familiarity with OpenROAD and other automated RTL-to-GDSII flows
  • Ability to program with Python or another scripting language.

We encourage you to apply even if you do not believe you meet every single qualification.

How we're different:

Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.

We are a fully in-person team in Cupertino, and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.

Benefits:

  • Full medical, dental, and vision packages, with 100% of premium covered, 90% for dependents
  • Housing subsidy of $2,000/month for those living within walking distance of the office
  • Daily lunch and dinner in our office
  • Relocation support for those moving to Cupertino

Apply