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Physical Design Engineer Jobs in California (NOW HIRING)

Physical Design Engineer

San Jose, CA ยท On-site

$159K - $164K/yr

Position: Physical Design Engineer Location: San Jose, CA Hybrid Duration: 12 Months VISA: H-1, USC Position Overview We are seeking an experienced Physical Design Engineer to support the ...

Physical Design Engineer

San Jose, CA ยท On-site

$70 - $80/hr

Physical Design Engineer Location: San Jose, CA Hybrid Duration: 12 Months VISA: H-1, GC, USC is okay C2C Position Overview We are seeking an experienced Physical Design Engineer to support the ...

Physical Design Engineer

Cupertino, CA ยท On-site

$167K - $172K/yr

We have an opportunity for a forward-thinking and unusually hardworking Physical Design Engineer. As a member of our wide-ranging group, you will have the rare and great opportunity to craft upcoming ...

Physical Design Engineer

San Francisco, CA ยท On-site

$160K - $164K/yr

We have an opportunity for a forward-thinking and unusually hardworking Physical Design Engineer. As a member of our wide-ranging group, you will have the rare and great opportunity to craft upcoming ...

Physical Design Engineer

Cupertino, CA ยท On-site

$167K - $172K/yr

We have an opportunity for a forward-thinking and unusually hardworking Physical Design Engineer. As a member of our wide-ranging group, you will have the rare and great opportunity to craft upcoming ...

Physical Design Engineer

Cupertino, CA ยท On-site

$167K - $172K/yr

We have an opportunity for a forward-thinking and unusually hardworking Physical Design Engineer. As a member of our wide-ranging group, you will have the rare and great opportunity to craft upcoming ...

Physical Design Engineer

Cupertino, CA ยท On-site

$167K - $172K/yr

We have an opportunity for a forward-thinking and unusually hardworking Physical Design Engineer. As a member of our wide-ranging group, you will have the rare and great opportunity to craft upcoming ...

Physical Design Engineer.

San Diego, CA ยท On-site

$144K - $148K/yr

Hello, Tittle-Physical Design Engineer Location- San Diego, California, San Jose, CA and Irvine, CA Job Type- Fulltime Physical Design Engineer We are looking for humble geniuses, who believe that ...

Physical Design Engineer

Cupertino, CA ยท On-site

$167K - $172K/yr

We have an opportunity for a forward-thinking and unusually hardworking Physical Design Engineer. As a member of our wide-ranging group, you will have the rare and great opportunity to craft upcoming ...

Physical Design Engineer

San Francisco, CA ยท On-site

$160K - $164K/yr

We have an opportunity for a forward-thinking and unusually hardworking Physical Design Engineer. As a member of our wide-ranging group, you will have the rare and great opportunity to craft upcoming ...

Physical Design Engineer

San Francisco, CA ยท On-site

$160K - $164K/yr

We have an opportunity for a forward-thinking and unusually hardworking Physical Design Engineer. As a member of our wide-ranging group, you will have the rare and great opportunity to craft upcoming ...

Physical Design Engineer

San Francisco, CA ยท On-site

$160K - $164K/yr

We have an opportunity for a forward-thinking and unusually hardworking Physical Design Engineer. As a member of our wide-ranging group, you will have the rare and great opportunity to craft upcoming ...

Physical Design Engineer

Sunnyvale, CA ยท On-site

$159K - $164K/yr

Physical Design Engineer Location:Sunnyvale, CA OR Austin,TX Duration: Long term experience: 5-18 years only ( No 18+ years profile) Job Overview: We are looking for a highly skilled Physical Design ...

Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII.","responsibilities":"Generate ...

Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII. Your responsibilities include ...

Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII.","responsibilities":"Your ...

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Showing results 1-20

Physical Design Engineer information

See California salary details

$93.8K

$139.6K

How much do physical design engineer jobs pay per year?

As of Aug 9, 2026, the average yearly pay for physical design engineer in California is $137,583.00, according to ZipRecruiter salary data. Most workers in this role earn between $134,200.00 and $138,200.00 per year, depending on experience, location, and employer.

What is a physical design engineer?

A Physical Design Engineer is responsible for transforming logical circuit designs into a physical layout that can be manufactured as an integrated circuit (IC). They focus on key aspects like floor planning, placement, clock tree synthesis (CTS), routing, and timing closure while ensuring power and performance optimization. They work with Electronic Design Automation (EDA) tools and collaborate with front-end designers to meet design specifications. The role requires proficiency in tools such as Cadence, Synopsys, or Mentor Graphics and knowledge of processes like ASIC or SoC design.

What are the key skills and qualifications needed to thrive as a physical design engineer?

To thrive as a Physical Design Engineer, you need a solid background in electrical engineering, experience with ASIC or SoC design methodologies, and a deep understanding of digital circuit fundamentals. Proficiency with EDA tools like Synopsys, Cadence, or Mentor Graphics, as well as familiarity with scripting languages and industry certifications, is highly valued. Attention to detail, effective teamwork, and strong problem-solving skills are essential soft skills for this role. These qualifications are crucial as they enable efficient chip design, ensure successful project delivery, and foster productive collaboration in complex engineering environments.

What are the typical daily responsibilities of a physical design engineer?

As a Physical Design Engineer, your daily responsibilities typically include taking logical circuit designs and translating them into physical layouts, performing floorplanning, placement, and routing of blocks, and conducting timing closure and verification. You will use specialized EDA tools to ensure that designs meet performance, power, and area requirements, collaborating closely with design, verification, and manufacturing teams. The role also involves resolving design issues, optimizing chip layouts, and preparing design data for fabrication. Working in this position provides exposure to advanced technology nodes and the opportunity to contribute directly to the development of cutting-edge semiconductor products.

What are the most commonly searched types of Physical Design Engineer jobs in California? The most popular types of Physical Design Engineer jobs in California are:
What job categories do people searching Physical Design Engineer jobs in California look for? The top searched job categories for Physical Design Engineer jobs in California are:
What cities in California are hiring for Physical Design Engineer jobs? Cities in California with the most Physical Design Engineer job openings:
Infographic showing various Physical Design Engineer job openings in California as of August 2026, with employment types broken down into 1% As Needed, 68% Full Time, 26% Part Time, 3% Temporary, and 2% Contract. Highlights an 97% Physical, 1% Hybrid, and 2% Remote job distribution, with an average salary of $137,583 per year, or $66.1 per hour.

Physical Design Engineer

Search Tactics LLC

San Jose, CA โ€ข On-site

$159K - $164K/yr

Other

Posted 11 days ago


Job description

Position: Physical Design Engineer
Location: San Jose, CA Hybrid

Duration: 12 Months

VISA: H-1, USC

Position Overview

We are seeking an experienced Physical Design Engineer to support the implementation of high-performance semiconductor designs targeting advanced process technologies. This contract position will focus on synthesis, floorplanning, physical implementation, and performance optimization for complex, timing-sensitive designs while working closely with cross-functional engineering teams.

Key Responsibilities

Execute RTL synthesis for complex ASIC and SoC designs using Cadence Genus.

Optimize designs for power, performance, and area (PPA) throughout the synthesis and physical design flow.

Develop and improve floorplans using Cadence Innovus, ensuring efficient utilization and routing.

Collaborate with RTL, architecture, and design teams to provide feedback on timing, constraints, and implementation strategies.

Partner with physical implementation and place-and-route teams to achieve timing closure and design quality goals.

Analyze timing challenges, identify critical paths, and recommend design improvements to improve convergence.

Support physical implementation activities from synthesis through implementation while maintaining design quality and schedule objectives.

Required Qualifications

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related discipline.

5+ years of experience in ASIC or SoC Physical Design.

Hands-on expertise with Cadence Genus for synthesis and Cadence Innovus for floorplanning and implementation.

Experience working on large, high-performance semiconductor designs with demanding timing requirements.

Strong knowledge of synthesis, timing analysis, physical implementation, and PPA optimization.

Experience with advanced semiconductor process technologies such as 5nm, 3nm, or newer.

Excellent communication skills and the ability to work effectively with RTL, architecture, physical design, and implementation teams.

Preferred Qualifications

Experience supporting complex SoC, AI, HPC, or accelerator designs.

Strong understanding of timing closure methodologies and synthesis-to-implementation correlation.

Familiarity with advanced implementation flows, design constraints, and physical optimization techniques.

Proven ability to collaborate with globally distributed engineering teams to deliver successful silicon implementations.