ZipRecruiter

Log In

1

Physical Design Engineer Jobs in California (NOW HIRING)

Altera Corporation

Physical Design Engineer

San Jose, CA · On-site

$105K - $120K/yr

As a Physical Design Engineer, you will support block-level and/or top-level physical design implementation activities across FPGA product development. You will work closely with cross-functional ...

Altera

Physical Design Engineer

San Jose, CA · On-site

$105K - $120K/yr

As a Physical Design Engineer, you will support block-level and/or top-level physical design implementation activities across FPGA product development. You will work closely with cross-functional ...

Apple

Physical Design Engineer

San Francisco, CA · On-site

$160K - $164K/yr

We have an opportunity for a forward-thinking and unusually hardworking Physical Design Engineer. As a member of our wide-ranging group, you will have the rare and great opportunity to craft upcoming ...

Apple

Physical Design Engineer

Cupertino, CA · On-site

$167K - $172K/yr

We have an opportunity for a forward-thinking and unusually hardworking Physical Design Engineer. As a member of our wide-ranging group, you will have the rare and great opportunity to craft upcoming ...

Apple

Physical Design Engineer

Cupertino, CA · On-site

$167K - $172K/yr

We have an opportunity for a forward-thinking and unusually hardworking Physical Design Engineer. As a member of our wide-ranging group, you will have the rare and great opportunity to craft upcoming ...

Apple

Physical Design Engineer

Cupertino, CA · On-site

$167K - $172K/yr

We have an opportunity for a forward-thinking and unusually hardworking Physical Design Engineer. As a member of our wide-ranging group, you will have the rare and great opportunity to craft upcoming ...

Apple

Physical Design Engineer

Cupertino, CA · On-site

$167K - $172K/yr

We have an opportunity for a forward-thinking and unusually hardworking Physical Design Engineer. As a member of our wide-ranging group, you will have the rare and great opportunity to craft upcoming ...

Apple

Physical Design Engineer

San Francisco, CA · On-site

$160K - $164K/yr

We have an opportunity for a forward-thinking and unusually hardworking Physical Design Engineer. As a member of our wide-ranging group, you will have the rare and great opportunity to craft upcoming ...

Apple

Physical Design Engineer

San Francisco, CA · On-site

$160K - $164K/yr

We have an opportunity for a forward-thinking and unusually hardworking Physical Design Engineer. As a member of our wide-ranging group, you will have the rare and great opportunity to craft upcoming ...

Apple

Physical Design Engineer

Cupertino, CA · On-site

$167K - $172K/yr

We have an opportunity for a forward-thinking and unusually hardworking Physical Design Engineer. As a member of our wide-ranging group, you will have the rare and great opportunity to craft upcoming ...

Apple

Physical Design Engineer

San Francisco, CA · On-site

$160K - $164K/yr

We have an opportunity for a forward-thinking and unusually hardworking Physical Design Engineer. As a member of our wide-ranging group, you will have the rare and great opportunity to craft upcoming ...

Apple

Physical Design Engineer

Cupertino, CA

$129K - $225K/yr

Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII.","responsibilities":"Generate ...

iFlow Inc

Physical Design Engineer

Sunnyvale, CA · On-site

$159K - $164K/yr

Physical Design Engineer Location:Sunnyvale, CA OR Austin,TX Duration: Long term experience: 5-18 years only ( No 18+ years profile) Job Overview: We are looking for a highly skilled Physical Design ...

Apple

Physical Design Engineer

Bodega Bay, CA

$150K - $277K/yr

Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII. Your responsibilities include ...

Apple

Physical Design Engineer

Cupertino, CA

$184K - $324K/yr

Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII. Your responsibilities include ...

next page

Showing results 1-20

All JobsPhysical Design Engineer JobsPhysical Design Engineer Jobs in California

Physical Design Engineer information

See California salary details

$93.8K

$139.6K

How much do physical design engineer jobs pay per year?

As of Jul 17, 2026, the average yearly pay for physical design engineer in California is $137,583.00, according to ZipRecruiter salary data. Most workers in this role earn between $134,200.00 and $138,200.00 per year, depending on experience, location, and employer.

What is a Physical Design Engineer job?

A Physical Design Engineer is responsible for transforming logical circuit designs into a physical layout that can be manufactured as an integrated circuit (IC). They focus on key aspects like floor planning, placement, clock tree synthesis (CTS), routing, and timing closure while ensuring power and performance optimization. They work with Electronic Design Automation (EDA) tools and collaborate with front-end designers to meet design specifications. The role requires proficiency in tools such as Cadence, Synopsys, or Mentor Graphics and knowledge of processes like ASIC or SoC design.

What are the key skills and qualifications needed to thrive in the Physical Design Engineer position, and why are they important?

To thrive as a Physical Design Engineer, you need a solid background in electrical engineering, experience with ASIC or SoC design methodologies, and a deep understanding of digital circuit fundamentals. Proficiency with EDA tools like Synopsys, Cadence, or Mentor Graphics, as well as familiarity with scripting languages and industry certifications, is highly valued. Attention to detail, effective teamwork, and strong problem-solving skills are essential soft skills for this role. These qualifications are crucial as they enable efficient chip design, ensure successful project delivery, and foster productive collaboration in complex engineering environments.

What are the typical daily responsibilities of a Physical Design Engineer?

As a Physical Design Engineer, your daily responsibilities typically include taking logical circuit designs and translating them into physical layouts, performing floorplanning, placement, and routing of blocks, and conducting timing closure and verification. You will use specialized EDA tools to ensure that designs meet performance, power, and area requirements, collaborating closely with design, verification, and manufacturing teams. The role also involves resolving design issues, optimizing chip layouts, and preparing design data for fabrication. Working in this position provides exposure to advanced technology nodes and the opportunity to contribute directly to the development of cutting-edge semiconductor products.

What are the most commonly searched types of Physical Design Engineer jobs in California? The most popular types of Physical Design Engineer jobs in California are:
What are popular job titles related to Physical Design Engineer jobs in California? For Physical Design Engineer jobs in California, the most frequently searched job titles are:
What job categories do people searching Physical Design Engineer jobs in California look for? The top searched job categories for Physical Design Engineer jobs in California are:
What cities in California are hiring for Physical Design Engineer jobs? Cities in California with the most Physical Design Engineer job openings:
What are popular job titles related to Physical Design Engineer jobs in CA? For Physical Design Engineer jobs in CA, the most frequently searched job titles are:
Physical Design Engineer jobs near you
Infographic showing various Physical Design Engineer job openings in California as of July 2026, with employment types broken down into 87% Full Time, 9% Part Time, 1% Temporary, and 3% Contract. Highlights an 87% Physical, 3% Hybrid, and 10% Remote job distribution, with an average salary of $137,583 per year, or $66.1 per hour.
Physical Design Engineer

Physical Design Engineer

Altera Corporation

San Jose, CA • On-site

$105K - $120K/yr

Full-time

This job post has expired today. Applications are no longer accepted.

Job description

Job Details:
Job Description:
About Altera
At Altera™, our independence as the world's largest pure-play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry-leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster, invest deeper, and partner more closely-empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry.
About the Role
Altera is looking for a Physical Design Engineer to join our Silicon Engineering organization.
In this role, you will contribute to the physical implementation of next-generation FPGA products, partnering closely with architecture, RTL design, DFT, timing, power, and verification teams to help deliver high-quality silicon. This is an excellent opportunity for an early-career engineer or recent graduate with a Master's degree who is looking to grow technical depth in physical design and backend implementation in a fast-paced semiconductor environment.
As a Physical Design Engineer, you will support block-level and/or top-level physical design implementation activities across FPGA product development. You will work closely with cross-functional teams to help optimize designs for timing, power, area, and manufacturability while contributing to the successful delivery of high-quality silicon.
Responsibilities
Other responsibilities of the Physical Design Engineer include but are not limited to:
  • Support block-level and/or top-level physical design implementation for FPGA and ASIC-style designs, including floorplanning, placement, clock tree synthesis, routing, and physical verification.
  • Work with senior physical design engineers to optimize designs for timing, power, area, congestion, and routability.
  • Participate in implementation tasks across the physical design flow, including netlist handoff, constraints setup, synthesis/physical design handoff, and signoff readiness.
  • Run and analyze timing, power, congestion, and design rule reports to identify issues and support closure activities.
  • Collaborate with RTL, design, DFT, CAD, and verification teams to resolve design and flow issues impacting physical implementation.
  • Support static timing analysis (STA), timing closure, and engineering change order (ECO) implementation activities.
  • Help debug physical design issues related to setup/hold violations, clocking, congestion, IR drop, or design rule violations.
  • Assist with physical verification tasks including DRC/LVS checks and design signoff preparation.
  • Develop and maintain scripts and automation to improve physical design productivity and flow efficiency.
  • Participate in silicon bring-up support and post-silicon debug activities as needed in partnership with cross-functional teams.

Salary Range
The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.
$105,000 - $120,000 USD
We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.
Qualifications:
Minimum Qualifications
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related engineering field with 2+ years of industry experience in physical design, ASIC/SoC backend implementation, or a related semiconductor engineering role, including experience in the following:
  • Physical design fundamentals including floorplanning, placement, clock tree synthesis (CTS), routing, timing closure, and physical verification.
  • Experience with industry-standard physical design and signoff tools such as Cadence Innovus, Synopsys ICC2, PrimeTime, Fusion Compiler, or similar tools.
  • Understanding of static timing analysis (STA), timing constraints, setup/hold concepts, and timing closure methodologies.
  • Experience reviewing and debugging timing, congestion, area, and power reports.
  • Familiarity with physical verification concepts including DRC/LVS and signoff quality checks.
  • Exposure to scripting or automation using Tcl, Python, Perl, or similar languages.
  • Knowledge of semiconductor design flows, from RTL handoff through physical implementation and signoff.
  • Strong understanding of digital design fundamentals and CMOS/VLSI concepts.

Preferred Qualifications
  • Master's degree in Electrical Engineering, Computer Engineering, or related field.
  • Experience with advanced-node physical design methodologies and low-power implementation concepts.
  • Exposure to FPGA, SoC, or high-performance semiconductor product development.
  • Familiarity with power planning, IR drop analysis, signal integrity, electromigration (EM) analysis, or physical signoff flows.
  • Experience working in Linux/Unix-based development environments.
  • Strong problem-solving skills and the ability to work effectively in a collaborative team environment.

Job Type:
Regular
Shift:
Shift 1 (United States of America)
Primary Location:
San Jose, California, United States
Additional Locations:
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Apply