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Soc Physical Design Engineer Jobs (NOW HIRING)

Apple

SoC Physical Design Engineer, PnR

San Jose, CA · On-site

$159K - $164K/yr

... physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC ... Preferred Qualifications MS in Electrical/Electronics/Computer Engineering or related field.

Apple

SoC Physical Design Engineer, PnR

San Diego, CA · On-site

$144K - $148K/yr

... physical design construction and analysis flows and methodology Preferred Qualifications MS in Electrical/Electronics/Computer Engineering or related field Experience with large SOC designs (>20M ...

Apple

SoC Physical Design Engineer, PnR

Beaverton, OR · On-site

$141K - $145K/yr

... physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC ... Engineering or related field. Experience with partition level P&R implementation including ...

Qualcomm

Staff SOC Physical Design Engineer

Austin, TX · On-site

$161.18 - $210/hr

... Physical Design Flow for high-speed DDR, graphics, and other SoC components, focusing on power ... Provide schedules and support cross‑functional engineering effort to drive signoff closure for ...

Apple

SoC Physical Design Engineer, PnR

Beaverton, OR · On-site

$141K - $145K/yr

... physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC ... Preferred Qualifications MS in Electrical/Electronics/Computer Engineering or related field.

Apple

SoC Physical Design Engineer, PnR

San Jose, CA

$184K - $324K/yr

... physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC ... Preferred Qualifications MS in Electrical/Electronics/Computer Engineering or related field.

Qualcomm

Senior SOC Physical Design Engineer

Austin, TX · On-site

$124 - $173/hr

Engineering Group, Engineering Group > ASICS Engineering General Summary: This individual ... Design Flow of high-speed DDR, graphics, physical verification flows, micro-architecture, SOC ...

Qualcomm

Senior SOC Physical Design Engineer

Austin, TX · On-site

$124K - $173K/yr

Engineering Group, Engineering Group > ASICS Engineering General Summary: This individual ... Design Flow of high-speed DDR, graphics, physical verification flows, micro-architecture, SOC ...

Apple

SoC Physical Design Engineer, PnR

San Diego, CA

$175K - $308K/yr

... physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC ... Preferred Qualifications MS in Electrical/Electronics/Computer Engineering or related field ...

Apple

SoC Physical Design Engineer, PnR

San Jose, CA

$184K - $324K/yr

... physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC ... Preferred Qualifications MS in Electrical/Electronics/Computer Engineering or related field.

Nutanix

Staff SOC Physical Design Engineer

Austin, TX · On-site

$152 - $210/hr

Engineering Group, Engineering Group > ASICS EngineeringGeneral Summary:This individual leads ... Design Flow of high-speed DDR, graphics, physical verification flows, micro-architecture, SOC ...

New

Qualcomm

Staff SOC Physical Design Engineer

Austin, TX · On-site

$152K - $210K/yr

Engineering Group, Engineering Group > ASICS Engineering General Summary: This individual leads ... Design Flow of high-speed DDR, graphics, physical verification flows, micro-architecture, SOC ...

Ralliant

ASIC Physical Design Engineer

Boulder, CO · On-site

$148.90 - $276.50/hr

ASIC Physical Design Engineer At Tektronix, we believe innovation starts with our customer. This ... In this role, you will work on all aspects of physical design and implementation of SOC devices ...

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Soc Physical Design Engineer information

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$95K

$141.5K

How much do soc physical design engineer jobs pay per year?

As of Aug 22, 2026, the average yearly pay for soc physical design engineer in the United States is $139,408.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $140,000.00 per year, depending on experience, location, and employer.

What is a SoC Physical Design Engineer?

SoC Physical Design Engineers are professionals who specialize in the layout and implementation of System-on-Chip (SoC) designs at the physical level. They are responsible for translating logical circuit designs into physical layouts that can be manufactured on silicon chips. Their tasks include floorplanning, placement, routing, timing analysis, and ensuring design for manufacturability. These engineers work closely with other teams to optimize power, performance, and area (PPA) while meeting strict technical specifications.

What skills and qualifications are needed to be a SoC Physical Design Engineer?

To thrive as a SoC Physical Design Engineer, you need a solid background in electrical engineering, digital logic design, and ASIC/FPGA development, usually supported by a relevant degree. Proficiency with EDA tools such as Cadence, Synopsys, and Mentor Graphics, as well as understanding of scripting languages like TCL and Perl, is typically required. Attention to detail, problem-solving skills, and effective teamwork are crucial soft skills for excelling in this role. These competencies ensure precise, efficient chip layouts that meet performance, power, and area targets in complex semiconductor projects.

What challenges do SoC Physical Design Engineers face during the tape-out phase, and how can they be addressed?

SoC Physical Design Engineers often encounter challenges such as meeting tight timing closure, managing power consumption, and resolving congestion during the tape-out phase. These issues require close collaboration with verification, synthesis, and DFT teams to iteratively optimize the physical layout and ensure all design constraints are satisfied. Effective use of EDA tools, proactive communication, and attention to detail are essential to address last-minute design rule violations and to deliver a high-quality, manufacturable chip on schedule.
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Soc Physical Design Engineer jobs near you
Infographic showing various Soc Physical Design Engineer job openings in the United States as of August 2026, with employment types broken down into 1% As Needed, 76% Full Time, 18% Part Time, 1% Temporary, 3% Contract, and 1% Nights. Highlights an 97% Physical, 1% Hybrid, and 2% Remote job distribution, with an average salary of $139,408 per year, or $67 per hour.

SoC Physical Design Engineer, PnR

Apple

San Jose, CA • On-site

$159K - $164K/yr

Full-time

Re-posted 4 days ago

Apple rating

8.0

Company rating: 8.0 out of 10

Based on 677 frontline employees who took The Breakroom Quiz

7th of 30 rated technology retailers

Job description

Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hardworking people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next groundbreaking Apple product!
In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC utilizing innovative process technology.
Description
• Work with the logic design team to understand partition architecture and drive physical aspects early in the design cycle.
• Complete netlist to GDS2 implementation for partition(s) meeting schedule and design goals.
• Timing, physical and electrical verification, and driving the signoff closure for the partitions.
• Resolve and improve design and flow issues related to physical design, identify potential solutions, and drive execution.
• Drive optimization of PnR partitions, to achieve best Power/Performance/Area.
Minimum Qualifications
Minimum BS and 10+ years of relevant industry experience.
Knowledge of partition level P&R implementation including floorplanning, clock and power distribution, timing closure, physical and electrical verification.
Knowledge of physical design construction and analysis flows and methodology.
Experience with industry standard tools, understanding their capabilities and underlying algorithms.
Familiar with typical SOC issues such as multiple voltage and clock domains and mixed signal block integration.
Preferred Qualifications
MS in Electrical/Electronics/Computer Engineering or related field.
Experience with large SOC designs (>20M gates) with frequencies in excess of 1GHZ.
Familiar with various process-related design issues including Design for Yield and Manufacturability and multi-vt strategies.
From a CAD perspective, experience with floorplanning tools, P&R flows, global timing verification, and physical design verification flows.
Ability to adhere to stringent schedule and die size requirements.

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About Apple

Sourced by ZipRecruiter

Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.

Industry

Computer and electronic product manufacturing

Company size

10,000+ Employees

Headquarters location

Cupertino, CA, US

Year founded

1976

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