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Soc Physical Design Engineer Jobs (NOW HIRING)

Carman Solutions Group

Physical Design Manager

Santa Clara, CA · On-site

$159K - $164K/yr

... Engineer to lead end-to-end implementation and optimization of advanced SoC designs. The ideal candidate will have strong expertise in physical implementation, timing convergence, low-power design ...

Qualcomm

Staff SOC Physical Design Engineer

Austin, TX · On-site

$152K - $210K/yr

Engineering Group, Engineering Group > ASICS Engineering General Summary: This individual leads ... Design Flow of high-speed DDR, graphics, physical verification flows, micro-architecture, SOC ...

Ralliant

ASIC Physical Design Engineer

Boulder, CO · On-site

$141K - $145K/yr

ASIC Physical Design Engineer At Tektronix, we believe innovation starts with our customer. This ... In this role, you will work on all aspects of physical design and implementation of SOC devices ...

Apple Inc.

$165K - $292K/yr

SoC Physical Design Engineer, STA/Timing Waltham, Massachusetts, United States Hardware Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services ...

Apple

SoC Physical Design Engineer, PnR

Beaverton, OR · On-site

$141K - $145K/yr

In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC utilizing innovative process ...

Apple

SoC Physical Design Engineer, PnR

San Jose, CA · On-site

$159K - $164K/yr

In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC utilizing innovative process ...

Apple

SoC Physical Design Engineer, PnR

San Diego, CA · On-site

$144K - $148K/yr

In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC utilizing innovative process ...

Apple

SoC Physical Design Engineer, PnR

Beaverton, OR

$141K - $145K/yr

In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC utilizing innovative process ...

Apple

SoC Physical Design Engineer, PnR

San Jose, CA · On-site

$159K - $164K/yr

In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC utilizing innovative process ...

Altera Corporation

Physical Design Engineer

San Jose, CA · On-site

$118K - $169K/yr

About the Role As a Physical Design Engineer at Altera, you will contribute to the physical implementation of FPGA/SoC designs, working with experienced engineers across the backend design flow from ...

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$95K

$141.5K

How much do soc physical design engineer jobs pay per year?

As of Sep 12, 2026, the average yearly pay for soc physical design engineer in the United States is $139,408.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $140,000.00 per year, depending on experience, location, and employer.

What is a SoC Physical Design Engineer?

SoC Physical Design Engineers are professionals who specialize in the layout and implementation of System-on-Chip (SoC) designs at the physical level. They are responsible for translating logical circuit designs into physical layouts that can be manufactured on silicon chips. Their tasks include floorplanning, placement, routing, timing analysis, and ensuring design for manufacturability. These engineers work closely with other teams to optimize power, performance, and area (PPA) while meeting strict technical specifications.

What skills and qualifications are needed to be a SoC Physical Design Engineer?

To thrive as a SoC Physical Design Engineer, you need a solid background in electrical engineering, digital logic design, and ASIC/FPGA development, usually supported by a relevant degree. Proficiency with EDA tools such as Cadence, Synopsys, and Mentor Graphics, as well as understanding of scripting languages like TCL and Perl, is typically required. Attention to detail, problem-solving skills, and effective teamwork are crucial soft skills for excelling in this role. These competencies ensure precise, efficient chip layouts that meet performance, power, and area targets in complex semiconductor projects.

What challenges do SoC Physical Design Engineers face during the tape-out phase, and how can they be addressed?

SoC Physical Design Engineers often encounter challenges such as meeting tight timing closure, managing power consumption, and resolving congestion during the tape-out phase. These issues require close collaboration with verification, synthesis, and DFT teams to iteratively optimize the physical layout and ensure all design constraints are satisfied. Effective use of EDA tools, proactive communication, and attention to detail are essential to address last-minute design rule violations and to deliver a high-quality, manufacturable chip on schedule.
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Soc Physical Design Engineer jobs near you
Infographic showing various Soc Physical Design Engineer job openings in the United States as of September 2026, with employment types broken down into 2% As Needed, 73% Full Time, 20% Part Time, 1% Temporary, 3% Contract, and 1% Nights. Highlights an 96% Physical, 1% Hybrid, and 3% Remote job distribution, with an average salary of $139,408 per year, or $67 per hour.

Physical Design Manager

Santa Clara, CA • On-site

Carman Solutions Group
51 - 200 employees
Learn more about Carman Solutions Groupexternal

$159K - $164K/yr

Full-time

Posted 8 days ago

Job description

Role- Physical Design ManagerLocation- San Jose, CA (Onsite)
Job Type- Fulltime
Role Overview

We are seeking a highly experienced Physical Design Engineer to lead end-to-end implementation and optimization of advanced SoC designs. The ideal candidate will have strong expertise in physical implementation, timing convergence, low-power design, and advanced semiconductor process technologies, along with the ability to drive methodology improvements and collaborate across engineering teams.

Key Responsibilities
  • Own the physical implementation lifecycle from netlist to GDSII, including synthesis, floorplan development, placement, clock-tree implementation, routing, and final timing/signoff closure.
  • Drive physical design optimization for advanced-node technologies (5nm and below), with a strong focus on performance, power, and area.
  • Implement and debug low-power architectures using UPF, including power-domain integration and related SoC-level challenges.
  • Analyze and resolve complex issues involving timing constraints, SDC, hierarchical integration, and UPF propagation across IP/SoC boundaries.
  • Develop and enhance automation and productivity solutions using Tcl, Python, Perl, and/or Shell scripting.
  • Work closely with RTL, STA, power, DFT, IP, methodology, and other cross-functional teams to achieve design milestones and tape-out readiness.
  • Support physical signoff activities, including timing, power integrity, physical verification, and design quality checks.
  • Identify opportunities to improve implementation methodologies, flows, and overall design efficiency.
  • Provide technical leadership and mentorship to junior engineers and contribute to team development.
Required Qualifications
  • 10+ years of industry experience in semiconductor physical design, implementation, and timing closure.
  • Bachelor’s degree in Computer Engineering, Computer Science, Electrical Engineering, or a related technical discipline, or equivalent industry experience.
  • Proven experience with RTL-to-GDSII implementation and successful tape-outs using 5nm or more advanced process technologies.
  • Strong understanding of SoC physical design, including floorplanning, placement optimization, clock and power network implementation, routing, and timing convergence.
  • Hands-on experience with industry-standard EDA tools such as Synopsys Design Compiler/ICC2/PrimeTime, Cadence Genus/Innovus, Ansys RedHawk/Voltus, and Calibre or equivalent tools.
  • Solid understanding of advanced process-node effects and their impact on physical implementation, timing, power, and layout quality.
  • Practical knowledge of low-power implementation and UPF-based power intent management.
  • Strong scripting and automation capabilities using Tcl, Python, Perl, or Shell.
  • Demonstrated ability to lead technical discussions and effectively collaborate with cross-functional engineering teams, IP teams, and external EDA partners.
  • Strong problem-solving, communication, ownership, and mentoring skills.