SoC Physical Design Engineer, PnR
$142K - $263K/yr
In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC utilizing innovative process ...
SoC Physical Design Engineer, PnR
$142K - $263K/yr
In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC utilizing innovative process ...
SoC Physical Design Engineer, PnR
San Jose, CA · On-site
$159K - $164K/yr
In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC utilizing innovative process ...
SoC Physical Design Engineer, PnR
San Jose, CA · On-site
$159K - $164K/yr
In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC utilizing innovative process ...
SoC Physical Design Engineer, STA/Timing
$141K - $145K/yr
... physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC ... Programming skills with Perl and TCL.
SoC Physical Design Engineer, STA/Timing
$141K - $145K/yr
... physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC ... Programming skills with Perl and TCL.
SoC Physical Design Engineer, STA/Timing
Waltham, MA · On-site
$146K - $151K/yr
... physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC ... Programming skills with Perl and TCL. Preferred Qualifications Hands-on experience in STA. Familiar ...
SoC Physical Design Engineer, STA/Timing
Waltham, MA · On-site
$146K - $151K/yr
... physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC ... Programming skills with Perl and TCL. Preferred Qualifications Hands-on experience in STA. Familiar ...
As a Physical Electrical Analysis Engineer on our SoC team, you will be driving the electrical analysis and verification of an SoC. Description - As a member of our physical design team, you will be ...
As a Physical Electrical Analysis Engineer on our SoC team, you will be driving the electrical analysis and verification of an SoC. Description - As a member of our physical design team, you will be ...
SoC Physical Design Engineer, PnR
$150K - $277K/yr
In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC utilizing innovative process ...
SoC Physical Design Engineer, PnR
$150K - $277K/yr
In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC utilizing innovative process ...
SoC Physical Design Engineer, STA/Timing
Waltham, MA · On-site
$146K - $151K/yr
... physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC ... Minimum Qualifications Minimum BS and 10+ years of relevant industry experience Strong programming ...
SoC Physical Design Engineer, STA/Timing
Waltham, MA · On-site
$146K - $151K/yr
... physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC ... Minimum Qualifications Minimum BS and 10+ years of relevant industry experience Strong programming ...
SoC Physical Design Engineer, STA/Timing
San Jose, CA · On-site
$159K - $164K/yr
... physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SoC ... Good programming skills with Perl and TCL. Experience with large design STA and Timing Closure.
SoC Physical Design Engineer, STA/Timing
San Jose, CA · On-site
$159K - $164K/yr
... physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SoC ... Good programming skills with Perl and TCL. Experience with large design STA and Timing Closure.
SoC Physical Design Engineer, STA/Timing
$134K - $138K/yr
... physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC ... Programming skills with Perl and TCL.
SoC Physical Design Engineer, STA/Timing
$134K - $138K/yr
... physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC ... Programming skills with Perl and TCL.
SoC Physical Design Engineer, STA/Timing
$141K - $145K/yr
... physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SoC ... Good programming skills with Perl and TCL. Experience with large design STA and Timing Closure.
SoC Physical Design Engineer, STA/Timing
$141K - $145K/yr
... physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SoC ... Good programming skills with Perl and TCL. Experience with large design STA and Timing Closure.
SoC Physical Design Engineer, Electrical Analysis
$129K - $194K/yr
As a Physical Electrical Analysis Engineer on our SoC team, you will be driving the electrical analysis and verification of an SoC. Description - As a member of our physical design team, you will be ...
SoC Physical Design Engineer, Electrical Analysis
$129K - $194K/yr
As a Physical Electrical Analysis Engineer on our SoC team, you will be driving the electrical analysis and verification of an SoC. Description - As a member of our physical design team, you will be ...
SoC Physical Design Engineer, STA/Timing
Austin, TX · On-site
$134K - $138K/yr
... physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC ... Programming skills with Perl and TCL. Preferred Qualifications Hands-on experience in STA. Familiar ...
SoC Physical Design Engineer, STA/Timing
Austin, TX · On-site
$134K - $138K/yr
... physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC ... Programming skills with Perl and TCL. Preferred Qualifications Hands-on experience in STA. Familiar ...
SoC Physical Design Engineer, STA/Timing
Beaverton, OR · On-site
$141K - $145K/yr
... physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC ... Programming skills with Perl and TCL. Preferred Qualifications Hands-on experience in STA. Familiar ...
SoC Physical Design Engineer, STA/Timing
Beaverton, OR · On-site
$141K - $145K/yr
... physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC ... Programming skills with Perl and TCL. Preferred Qualifications Hands-on experience in STA. Familiar ...
SoC Physical Design Engineer, Electrical Analysis
$150K - $277K/yr
As a Physical Electrical Analysis Engineer on our SoC team, you will be driving the electrical analysis and verification of an SoC. Description - As a member of our physical design team, you will be ...
SoC Physical Design Engineer, Electrical Analysis
$150K - $277K/yr
As a Physical Electrical Analysis Engineer on our SoC team, you will be driving the electrical analysis and verification of an SoC. Description - As a member of our physical design team, you will be ...
SoC Physical Design Engineer, PnR
Waltham, MA · On-site
$146K - $151K/yr
We are seeking a seasoned Physical Design technical leader with deep expertise in high-performance ... Experience with large SOC designs (>20M gates) with frequencies in excess of 1GHZ. Shown ability to ...
SoC Physical Design Engineer, PnR
Waltham, MA · On-site
$146K - $151K/yr
We are seeking a seasoned Physical Design technical leader with deep expertise in high-performance ... Experience with large SOC designs (>20M gates) with frequencies in excess of 1GHZ. Shown ability to ...
SoC Physical Design Engineer, STA/Timing
$134K - $138K/yr
... physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC ... Programming skills with Perl and TCL.
SoC Physical Design Engineer, STA/Timing
$134K - $138K/yr
... physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC ... Programming skills with Perl and TCL.
SoC Physical Design Engineer, STA/Timing
San Diego, CA · On-site
$144K - $148K/yr
... physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC ... Programming skills with Perl and TCL. Preferred Qualifications Hands-on experience in STA. Familiar ...
SoC Physical Design Engineer, STA/Timing
San Diego, CA · On-site
$144K - $148K/yr
... physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC ... Programming skills with Perl and TCL. Preferred Qualifications Hands-on experience in STA. Familiar ...
SoC Physical Design Engineer, STA/Timing
San Diego, CA · On-site
$144K - $148K/yr
... physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC ... Programming skills with Perl and TCL. Preferred Qualifications Hands-on experience in STA. Familiar ...
SoC Physical Design Engineer, STA/Timing
San Diego, CA · On-site
$144K - $148K/yr
... physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC ... Programming skills with Perl and TCL. Preferred Qualifications Hands-on experience in STA. Familiar ...
SoC Physical Design Engineer, STA/Timing
San Diego, CA · On-site
$144K - $148K/yr
... physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC ... Programming skills with Perl and TCL. Preferred Qualifications Hands-on experience in STA. Familiar ...
SoC Physical Design Engineer, STA/Timing
San Diego, CA · On-site
$144K - $148K/yr
... physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC ... Programming skills with Perl and TCL. Preferred Qualifications Hands-on experience in STA. Familiar ...
SoC Physical Design Engineer, STA/Timing
Beaverton, OR · On-site
$141K - $145K/yr
... physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SoC ... Good programming skills with Perl and TCL. Experience with large design STA and Timing Closure.
SoC Physical Design Engineer, STA/Timing
Beaverton, OR · On-site
$141K - $145K/yr
... physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SoC ... Good programming skills with Perl and TCL. Experience with large design STA and Timing Closure.
Soc Physical Design Engineer information
See salary details
$95K - $99.2K
0% of jobs
$99.2K - $103.5K
0% of jobs
$103.5K - $107.7K
0% of jobs
$107.7K - $111.9K
0% of jobs
$111.9K - $116.1K
0% of jobs
$116.1K - $120.4K
0% of jobs
$120.4K - $124.6K
0% of jobs
$124.6K - $128.8K
0% of jobs
$128.8K - $133K
1% of jobs
$135.4K is the 25th percentile. Wages below this are outliers.
$133K - $137.3K
43% of jobs
The median wage is $137.7K / yr.
$137.3K - $141.5K
56% of jobs
$95K
$141.5K
How much do soc physical design engineer jobs pay per year?
As of Jul 11, 2026, the average yearly pay for soc physical design engineer in the United States is $139,408.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $140,000.00 per year, depending on experience, location, and employer.
What are SoC Physical Design Engineers?
SoC Physical Design Engineers are professionals who specialize in the layout and implementation of System-on-Chip (SoC) designs at the physical level. They are responsible for translating logical circuit designs into physical layouts that can be manufactured on silicon chips. Their tasks include floorplanning, placement, routing, timing analysis, and ensuring design for manufacturability. These engineers work closely with other teams to optimize power, performance, and area (PPA) while meeting strict technical specifications.
What are the key skills and qualifications needed to thrive as a SoC Physical Design Engineer, and why are they important?
To thrive as a SoC Physical Design Engineer, you need a solid background in electrical engineering, digital logic design, and ASIC/FPGA development, usually supported by a relevant degree. Proficiency with EDA tools such as Cadence, Synopsys, and Mentor Graphics, as well as understanding of scripting languages like TCL and Perl, is typically required. Attention to detail, problem-solving skills, and effective teamwork are crucial soft skills for excelling in this role. These competencies ensure precise, efficient chip layouts that meet performance, power, and area targets in complex semiconductor projects.
What are some common challenges faced by SoC Physical Design Engineers during the tape-out phase, and how can they be addressed?
SoC Physical Design Engineers often encounter challenges such as meeting tight timing closure, managing power consumption, and resolving congestion during the tape-out phase. These issues require close collaboration with verification, synthesis, and DFT teams to iteratively optimize the physical layout and ensure all design constraints are satisfied. Effective use of EDA tools, proactive communication, and attention to detail are essential to address last-minute design rule violations and to deliver a high-quality, manufacturable chip on schedule.
More about Soc Physical Design Engineer jobs
What cities are hiring for Soc Physical Design Engineer jobs? Cities with the most Soc Physical Design Engineer job openings:
What states have the most Soc Physical Design Engineer jobs? States with the most job openings for Soc Physical Design Engineer jobs include:
What job categories do people searching Soc Physical Design Engineer jobs look for? The top searched job categories for Soc Physical Design Engineer jobs are:
$142K - $263K/yr
Full-time
Medical, Dental, Retirement
Re-posted 27 days ago
Apple rating
8.1
Based on 670 frontline employees who took The Breakroom Quiz
5th of 30 rated technology retailers
Job description
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hardworking people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next groundbreaking Apple product!
In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC utilizing innovative process technology.
Description
• Work with the logic design team to understand partition architecture and drive physical aspects early in the design cycle.
• Complete netlist to GDS2 implementation for partition(s) meeting schedule and design goals.
• Timing, physical and electrical verification, and driving the signoff closure for the partitions.
• Resolve and improve design and flow issues related to physical design, identify potential solutions, and drive execution.
Preferred Qualifications
Ability to adhere to stringent schedule and die size requirements.
Experience with large SOC designs (>20M gates) with frequencies in excess of 1GHZ.
Experience with sub 10nm tech nodes.
Experience with industry standard tools, understanding their capabilities and underlying algorithms.
Strong communication skills.
Experience with physical design construction and analysis flows and methodology.
Minimum Qualifications
Minimum BS and 3+ years of relevant industry experience
Experience with partition level P&R implementation.
Experience with one or more of the following: floorplanning, clock and power distribution, timing closure, physical verification, electrical verification.
Pay & Benefits
At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $142,300 and $263,300, and your base pay will depend on your skills, qualifications, experience, and location.
Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC utilizing innovative process technology.
Description
• Work with the logic design team to understand partition architecture and drive physical aspects early in the design cycle.
• Complete netlist to GDS2 implementation for partition(s) meeting schedule and design goals.
• Timing, physical and electrical verification, and driving the signoff closure for the partitions.
• Resolve and improve design and flow issues related to physical design, identify potential solutions, and drive execution.
Preferred Qualifications
Ability to adhere to stringent schedule and die size requirements.
Experience with large SOC designs (>20M gates) with frequencies in excess of 1GHZ.
Experience with sub 10nm tech nodes.
Experience with industry standard tools, understanding their capabilities and underlying algorithms.
Strong communication skills.
Experience with physical design construction and analysis flows and methodology.
Minimum Qualifications
Minimum BS and 3+ years of relevant industry experience
Experience with partition level P&R implementation.
Experience with one or more of the following: floorplanning, clock and power distribution, timing closure, physical verification, electrical verification.
Pay & Benefits
At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $142,300 and $263,300, and your base pay will depend on your skills, qualifications, experience, and location.
Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
About Apple
Sourced by ZipRecruiter
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Cupertino, CA, US
Year founded
1976