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Soc Physical Design Engineer Jobs (NOW HIRING)

Ralliant

ASIC Physical Design Engineer

Boulder, CO · On-site

$141K - $145K/yr

ASIC Physical Design Engineer At Tektronix, we believe innovation starts with our customer. This ... In this role, you will work on all aspects of physical design and implementation of SOC devices ...

Apple

SoC Physical Design Engineer, PnR

Beaverton, OR · On-site

$141K - $145K/yr

In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC utilizing innovative process ...

Apple

SoC Physical Design Engineer, PnR

San Jose, CA · On-site

$159K - $164K/yr

In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC utilizing innovative process ...

Apple

SoC Physical Design Engineer, PnR

San Diego, CA · On-site

$144K - $148K/yr

In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC utilizing innovative process ...

Apple

SoC Physical Design Engineer, PnR

Beaverton, OR

$141K - $145K/yr

In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC utilizing innovative process ...

Apple

SoC Physical Design Engineer, PnR

San Jose, CA

$150K - $277K/yr

In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC utilizing innovative process ...

Apple

SoC Physical Design Engineer, PnR

San Jose, CA · On-site

$159K - $164K/yr

In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC utilizing innovative process ...

Apple

SoC Physical Design Engineer, PnR

Austin, TX · On-site

$134K - $138K/yr

We are seeking a seasoned Physical Design technical leader with deep expertise in high-performance ... Experience with large SOC designs (>20M gates) with frequencies in excess of 1GHZ. Shown ability to ...

Micron

Senior SOC Physical Design Engineer, HBM

Richardson, TX · On-site

$123K - $127K/yr

... Engineering, or a related field, or equivalent practical experience. * Minimum three to five years of experience in a related physical design or SoC implementation role. * Experience with signal ...

Altera

Senior Physical Design Engineer/Lead

San Jose, CA · On-site

$149.10 - $215/hr

Physical Design Engineer** at Altera, you will play a critical role in our backend implementation flow -- from RTL/netlist through to GDSII/tape-out for FPGA/SoC devices. You will interface with ...

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Soc Physical Design Engineer information

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$95K

$141.5K

How much do soc physical design engineer jobs pay per year?

As of Aug 22, 2026, the average yearly pay for soc physical design engineer in the United States is $139,408.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $140,000.00 per year, depending on experience, location, and employer.

What is a SoC Physical Design Engineer?

SoC Physical Design Engineers are professionals who specialize in the layout and implementation of System-on-Chip (SoC) designs at the physical level. They are responsible for translating logical circuit designs into physical layouts that can be manufactured on silicon chips. Their tasks include floorplanning, placement, routing, timing analysis, and ensuring design for manufacturability. These engineers work closely with other teams to optimize power, performance, and area (PPA) while meeting strict technical specifications.

What skills and qualifications are needed to be a SoC Physical Design Engineer?

To thrive as a SoC Physical Design Engineer, you need a solid background in electrical engineering, digital logic design, and ASIC/FPGA development, usually supported by a relevant degree. Proficiency with EDA tools such as Cadence, Synopsys, and Mentor Graphics, as well as understanding of scripting languages like TCL and Perl, is typically required. Attention to detail, problem-solving skills, and effective teamwork are crucial soft skills for excelling in this role. These competencies ensure precise, efficient chip layouts that meet performance, power, and area targets in complex semiconductor projects.

What challenges do SoC Physical Design Engineers face during the tape-out phase, and how can they be addressed?

SoC Physical Design Engineers often encounter challenges such as meeting tight timing closure, managing power consumption, and resolving congestion during the tape-out phase. These issues require close collaboration with verification, synthesis, and DFT teams to iteratively optimize the physical layout and ensure all design constraints are satisfied. Effective use of EDA tools, proactive communication, and attention to detail are essential to address last-minute design rule violations and to deliver a high-quality, manufacturable chip on schedule.
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Soc Physical Design Engineer jobs near you
Infographic showing various Soc Physical Design Engineer job openings in the United States as of August 2026, with employment types broken down into 1% As Needed, 76% Full Time, 18% Part Time, 1% Temporary, 3% Contract, and 1% Nights. Highlights an 97% Physical, 1% Hybrid, and 2% Remote job distribution, with an average salary of $139,408 per year, or $67 per hour.

SoC Physical Design Methodology Engineer

Apple Inc.

Austin, TX • On-site

$100 - $150/hr

Other

Re-posted 14 days ago

Apple rating

8.0

Company rating: 8.0 out of 10

Based on 677 frontline employees who took The Breakroom Quiz

7th of 30 rated technology retailers

Job description

SoC Physical Design Methodology Engineer

In this role, you will be directly involved in our physical design methodology efforts, collaborating right alongside our internal multi‑functional teams to ensure our SoCs achieve the optimal power, performance, and area (PPA) in the most efficient way possible. You will create and implement methodologies that improve the robustness, power, performance, and area (PPA) of our on‑chip interconnects. You will perform electrical analysis to understand how physical effects impact the performance of our designs. You will develop construction methodologies to help mitigate any PPA degradation found in silicon. You will help ensure our modeling of silicon is efficient and accurate by running our sign‑off flows and comparing results to measurements from silicon we create. You will collaborate with the standard cell team to identify new cells to improve PPA, yield, or engineering productivity. You will work with CAD and design teams to drive these improvements and updates in our production design flows in an effective and timely manner. You will verify theories by creating a strategy to verify them in silicon and apply the latest advances in data science and machine learning when needed in crafting these methodologies.

Minimum Qualifications
  • Bachelor's degree in Electrical Engineering, Computer Science, or related field with 3 years of experience.
Preferred Qualifications
  • Strong intellectual curiosity, with excellent communication skills.
  • Organized, a self‑starter, and adaptable to any challenge that comes up.
  • Physical design experience on SoC designs is a plus.
  • Experience working with advanced technology nodes.
  • Deep knowledge about interconnects, parasitic extraction, performance analysis, and how manufacturing effects make these non‑ideal. Extensive knowledge of power delivery and how power‑supplies noise impacts chip performance.
  • Understanding inductance effects and circuit design experience. Comfortable running and modifying Spice simulations.
  • Familiar with static timing analysis tools and methodologies and able to explain silicon behaviors.
  • Proven understanding of scripting languages such as Python and Tcl.
  • Experience with flow development for a large number of users on a tight schedule is a plus.

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EOO rights as an applicant.

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About Apple

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Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.

Industry

Computer and electronic product manufacturing

Company size

10,000+ Employees

Headquarters location

Cupertino, CA, US

Year founded

1976

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