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Physical Design Manager Jobs (NOW HIRING)

Physical Design Manager

Westborough, MA

$140.10K - $144.20K/yr

Communicate execution status, risks, and tradeoffs clearly to engineering leadership What We're Looking For Principal Physical Design Manager (PlayerCoach, HandsOn) About the Role We are looking for ...

Physical Design Engineer

Sunnyvale, CA · On-site

$159.60K - $164.30K/yr

Top-Level Physical Design: • Chip-Level Floorplanning & Hierarchical Design - Manage top-level layout planning, pin assignments, and cross-block optimizations. • Strong scripting experience. • ...

New

Physical Design Engineer

Sunnyvale, CA

$161.80K - $166.60K/yr

Top-Level Physical Design: • Chip-Level Floorplanning & Hierarchical Design - Manage top-level layout planning, pin assignments, and cross-block optimizations. • Strong scripting experience. • ...

Physical Design Engineer

Austin, TX

$134.80K - $138.70K/yr

Chip-Level Floorplanning & Hierarchical Design - Manage top-level layout planning, pin assignments, and cross-block optimizations. * Strong scripting experience. * Clock & Power Distribution - Design ...

Physical Design Engineer

Austin, TX

$134.80K - $138.70K/yr

Top-Level Physical Design: • Chip-Level Floorplanning & Hierarchical Design - Manage top-level layout planning, pin assignments, and cross-block optimizations. • Strong scripting experience. • ...

Chip-Level Floorplanning & Hierarchical Design - Manage top-level layout planning, pin assignments ... VLSI Physical Place and Route. Experience: 8-10 Years. The expected compensation for this role ...

Physical Design Engineer

Sunnyvale, TX · On-site

$60K - $148.50K/yr

Top-Level Physical Design: • Chip-Level Floorplanning & Hierarchical Design - Manage top-level layout planning, pin assignments, and cross-block optimizations. • Strong scripting experience. • ...

New

Engineer, Physical Design

San Jose, CA · On-site

$120K - $160K/yr

Physical Design Engineer: Location: San Jose (on-site) Ayar Labs is shattering AI data bottlenecks ... Please don't send candidates to Ayar Labs, and do not contact our managers. Ayar Labs is an Equal ...

Physical Design Engineer: Location: San Jose (on-site) Ayar Labs is shattering AI data bottlenecks ... Please don't send candidates to Ayar Labs, and do not contact our managers. Ayar Labs is an Equal ...

Physical Design Engineer

San Diego, CA

$144.40K - $148.60K/yr

We are 500+ employees in India and 250+ In US Clear visibility to senior management which helps for constant professional growth Title : Physical Design Engineer Location : San Diego,CA Type ...

Physical Design Engineer

San Jose, CA · On-site

$120K - $192K/yr

Resolve physical design issues related to chip integration and assembly ... Manage all cross functional interactions related to top level floorplanning, I/O and bump planning ...

Physical Design Engineer

San Jose, CA · On-site

$141.30K - $226K/yr

Resolve physical design issues related to chip integration and assembly ... Manage all cross functional interactions related to top level floorplanning, I/O and bump planning ...

Physical Design Engineer

Saratoga, CA · On-site

$210K - $250K/yr

Define the Physical Assembly of SOC. involving all aspects of physical design functions such as P&R ... Recruiting agencies are expressly instructed not to contact hiring managers, employees, or ...

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Physical Design Manager information

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$42K

$114.5K

$201.5K

How much do physical design manager jobs pay per year?

As of May 31, 2026, the average yearly pay for physical design manager in the United States is $114,491.00, according to ZipRecruiter salary data. Most workers in this role earn between $83,500.00 and $144,000.00 per year, depending on experience, location, and employer.

What is a Physical Design Manager job?

A Physical Design Manager oversees the physical implementation of integrated circuits (ICs), ensuring efficient design, timing closure, and power optimization. They lead a team of engineers responsible for tasks like floorplanning, place and route, clock tree synthesis, and signoff verification. Their role involves collaborating with design, verification, and manufacturing teams to meet project deadlines and performance targets. Strong technical expertise in EDA tools, process nodes, and industry standards is essential.

What are the key skills and qualifications needed to thrive in the Physical Design Manager position, and why are they important?

To thrive as a Physical Design Manager, you need a deep understanding of ASIC/SoC design flows, timing closure, floorplanning, and digital circuit fundamentals, often backed by a degree in electrical or computer engineering. Familiarity with EDA tools such as Cadence, Synopsys, or Mentor Graphics, and knowledge of industry standards like IEEE are crucial, while certifications in VLSI design can be advantageous. Strong leadership, project management abilities, and effective communication skills help in leading multidisciplinary teams and coordinating complex projects. These competencies ensure high-quality chip design delivery, efficient team performance, and on-time project completion in a fast-paced semiconductor environment.

What are some common challenges faced by Physical Design Managers, and how can they be addressed?

Physical Design Managers often encounter challenges such as managing tight project deadlines, achieving timing closure, and balancing trade-offs between power, performance, and area in chip designs. Coordination between multiple design teams and keeping up with evolving EDA tool technologies can also require effective communication and continuous learning. Proactive planning, strong technical mentorship, and fostering collaboration across teams help address these challenges. Staying up to date with industry advancements and encouraging a culture of open problem-solving are also key to overcoming common obstacles in this role.
What cities are hiring for Physical Design Manager jobs? Cities with the most Physical Design Manager job openings:
What are the most commonly searched types of Physical Design jobs? The most popular types of Physical Design jobs are:
What states have the most Physical Design Manager jobs? States with the most job openings for Physical Design Manager jobs include:
Infographic showing various Physical Design Manager job openings in the United States as of May 2026, with employment types broken down into 82% Full Time, 15% Part Time, 2% Contract, and 1% Nights. Highlights an 86% Physical, 3% Hybrid, and 11% Remote job distribution, with an average salary of $114,491 per year, or $55 per hour.
Physical Design Manager

Physical Design Manager

Marvell Technology, Inc.

Westborough, MA • On-site

$140.10K - $144.20K/yr

Full-time

Life, Retirement

Posted 21 days ago


Job description

About Marvell
Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
About Marvell
Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud, networking, and AI architectures, our innovative technology is enabling new possibilities-from high-performance compute to intelligent data movement at scale.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful, enduring innovation-above and beyond fleeting trends-Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
Built on decades of expertise and execution, Marvell's Custom Processor and ASIC Solutions organization delivers a differentiated approach through a best-in-class portfolio of data infrastructure intellectual property and flexible engagement models. Our custom silicon powers some of the most demanding workloads in the industry, spanning cloud data centers, networking, storage, and next-generation AI platforms.
In this role, you will contribute to both the physical design and methodology development for future generations of high-performance processor and accelerator silicon, implemented in leading-edge CMOS process technologies. These designs are directly targeted at AI training and inference, cloud compute, and high-bandwidth networking applications, where power, performance, and scalability are critical.
You will work at the intersection of advanced physical design, timing closure, and AI-driven compute demands, helping to enable custom silicon solutions that accelerate innovation across the data infrastructure ecosystem.
Work Location
This role is onsite at Marvell's Westborough, Massachusetts location. Remote or Hybrid opportunities are not offered at this time. Relocation assistance will be provided for qualified candidates.
What You Can Expect
Job Responsibilities
  • Serve as the primary technical owner for physical design and timing closure on assigned blocks, partitions, or subsystems
  • Perform hands-on physical design and timing analysis, including late-stage debug and convergence
  • Define and actively drive closure strategy, not just review results
  • Act as a key technical escalation point, stepping in directly when progress stalls
  • Lead and mentor a small team of PD engineers as a player-coach
  • Provide prioritization, technical direction, and day-to-day execution guidance
  • Coordinate closely with STA, RTL, CAD, and Program teams to resolve complex issues
  • Support hiring, onboarding, and ramp-up of new team members while maintaining technical ownership
  • Communicate execution status, risks, and tradeoffs clearly to engineering leadership

What We're Looking For
Principal Physical Design Manager (Player-Coach, Hands-On)
About the Role
We are looking for a Physical Design Mananger who will operate in a hands-on, execution-first player-coach role. This position combines direct technical contribution with first-line people leadership. The ideal candidate is someone who wants to stay deeply involved in physical design and timing closure while guiding a small team through critical execution phases.
This is not a pure people-management role. Success in this position is measured by delivery, convergence, and technical ownership, not by team size.
Technical Qualifications
  • Bachelor's degree in Computer Science, Electrical Engineering or related fields and 10-15 years of related professional experience or Master's degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5-10 years of experience or equivalent professional experience in lieu of a formal degree
  • Principal-level physical design expertise with a proven track record delivering timing-closed ASICs or complex SoCs
  • Demonstrated success in timing analysis and closure across multiple designs
  • Deep understanding of advanced timing concepts including SI, CDC, LVF, POCV, and related methodologies
  • Strong proficiency with PD and STA tools (e.g., Synopsys PrimeTime or equivalent), scripting, and UNIX/Linux environments
  • Strong written and verbal communication skills with the ability to articulate technical tradeoffs

Leadership Experience (Execution-Focused)
  • Experience leading PD engineers in a first-line, hands-on capacity
  • Proven ability to operate as a player-coach, contributing technically while guiding others
  • Experience mentoring engineers and developing PD talent through active engagement
  • Ability to coordinate execution across cross-functional teams with clear ownership and accountability

Nice to Have
  • Experience owning full-chip or large-subsystem PD and timing closure
  • Familiarity with timing methodology and flow development
  • Experience working with multi-site or globally distributed teams
  • Experience balancing FTE and contractor resources

Growth Opportunity
This role is scoped as an player-coach today, with the opportunity to grow into broader leadership influence over time, while remaining technically engaged.
Expected Base Pay Range (USD)
185,900 - 275,170, $ per annum
The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements
Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life's most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.
Interview Integrity
To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.
This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.
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