1

Physical Design Manager Jobs (NOW HIRING)

Physical Design Engineer

Sunnyvale, CA · On-site

$159K - $164K/yr

Top-Level Physical Design: • Chip-Level Floorplanning & Hierarchical Design - Manage top-level layout planning, pin assignments, and cross-block optimizations. • Strong scripting experience. • ...

$135K - $139K/yr

Join Intel as a Physical Design Engineer and play a pivotal role in shaping the future of cutting ... Our charter encompasses defining business strategy and roadmaps, product management, developing ...

Physical Design Engineer

Phoenix, AZ · On-site

$135K - $139K/yr

Join Intel as a Physical Design Engineer and play a pivotal role in shaping the future of custom IP ... Our charter encompasses defining business strategy and roadmaps, product management, developing ...

$135K - $139K/yr

Join Intel as a Physical Design Engineer and play a pivotal role in shaping the future of custom IP ... Our charter encompasses defining business strategy and roadmaps, product management, developing ...

Physical Design Engineer

Phoenix, AZ · On-site

$135K - $139K/yr

Join Intel as a Physical Design Engineer and play a pivotal role in shaping the future of cutting ... Our charter encompasses defining business strategy and roadmaps, product management, developing ...

Physical Design Engineer

San Diego, CA

$144K - $148K/yr

We are 500+ employees in India and 250+ In US Clear visibility to senior management which helps for constant professional growth Title : Physical Design Engineer Location : San Diego,CA Type ...

Physical Design Engineer

San Jose, CA · On-site

$141K - $226K/yr

Resolve physical design issues related to chip integration and assembly ... Manage all cross functional interactions related to top level floorplanning, I/O and bump planning ...

Physical Design Engineer

Saratoga, CA · On-site

$210K - $250K/yr

Define the Physical Assembly of SOC. involving all aspects of physical design functions such as P&R ... Recruiting agencies are expressly instructed not to contact hiring managers, employees, or ...

GPU Physical Verification Design Engineer

Austin, TX · On-site

$134K - $138K/yr

You will manage and resolve design and flow issues related to physical design, identify potential solutions and drive execution. You will need to communicate and drive the needs of Physical Design ...

Physical Design Engineer (7452)

San Jose, CA · On-site

$155K - $160K/yr

Join our dynamic Test Chip Physical Implementation team in San Jose, CA, and play a critical role ... management. * Extensive design optimization for power, performance, and area (PPA) targets.

next page

Showing results 1-20

Physical Design Manager information

See salary details

$42K

$114.5K

$201.5K

How much do physical design manager jobs pay per year?

As of Jul 21, 2026, the average yearly pay for physical design manager in the United States is $114,491.00, according to ZipRecruiter salary data. Most workers in this role earn between $83,500.00 and $144,000.00 per year, depending on experience, location, and employer.

What are some common challenges faced by Physical Design Managers, and how can they be addressed?

Physical Design Managers often encounter challenges such as managing tight project deadlines, achieving timing closure, and balancing trade-offs between power, performance, and area in chip designs. Coordination between multiple design teams and keeping up with evolving EDA tool technologies can also require effective communication and continuous learning. Proactive planning, strong technical mentorship, and fostering collaboration across teams help address these challenges. Staying up to date with industry advancements and encouraging a culture of open problem-solving are also key to overcoming common obstacles in this role.

What is a Physical Design Manager job?

A Physical Design Manager oversees the physical implementation of integrated circuits (ICs), ensuring efficient design, timing closure, and power optimization. They lead a team of engineers responsible for tasks like floorplanning, place and route, clock tree synthesis, and signoff verification. Their role involves collaborating with design, verification, and manufacturing teams to meet project deadlines and performance targets. Strong technical expertise in EDA tools, process nodes, and industry standards is essential.

What are the key skills and qualifications needed to thrive in the Physical Design Manager position, and why are they important?

To thrive as a Physical Design Manager, you need a deep understanding of ASIC/SoC design flows, timing closure, floorplanning, and digital circuit fundamentals, often backed by a degree in electrical or computer engineering. Familiarity with EDA tools such as Cadence, Synopsys, or Mentor Graphics, and knowledge of industry standards like IEEE are crucial, while certifications in VLSI design can be advantageous. Strong leadership, project management abilities, and effective communication skills help in leading multidisciplinary teams and coordinating complex projects. These competencies ensure high-quality chip design delivery, efficient team performance, and on-time project completion in a fast-paced semiconductor environment.

More about Physical Design Manager jobs
What cities are hiring for Physical Design Manager jobs? Cities with the most Physical Design Manager job openings:
What are the most commonly searched types of Physical Design jobs? The most popular types of Physical Design jobs are:
What states have the most Physical Design Manager jobs? States with the most job openings for Physical Design Manager jobs include:
Infographic showing various Physical Design Manager job openings in the United States as of July 2026, with employment types broken down into 89% Full Time, 8% Part Time, and 3% Contract. Highlights an 87% Physical, 3% Hybrid, and 10% Remote job distribution, with an average salary of $114,491 per year, or $55 per hour.
ASIC Digital Physical Design Manager

ASIC Digital Physical Design Manager

Keysight Technologies, Inc.

Colorado Springs, CO

$134K - $138K/yr

Other

Medical, Dental, Vision, Life, Retirement, PTO

Re-posted 21 days ago


Keysight Technologies rating

8.1

Company rating: 8.1 out of 10

Based on 20 frontline employees who took The Breakroom Quiz

42nd of 143 rated electronics manufacturers


Job description

Overview

Keysight is at the forefront of technology innovation, delivering breakthroughs and trusted insights in electronic design, simulation, prototyping, test, manufacturing, and optimization. Our ~15,000 employees create world-class solutions in communications, 5G, automotive, energy, quantum, aerospace, defense, and semiconductor markets for customers in over 100 countries. Learn more about what we do.

Our award-winning culture embraces a bold vision of where technology can take us and a passion for tackling challenging problems with industry-first solutions. We believe that when people feel a sense of belonging, they can be more creative, innovative, and thrive at all points in their careers.

This role sits within Keysight Laboratories—a globally recognized technology organization that enables Keysight to be first to market with breakthrough, highly differentiated solutions. Our team of senior engineers has delivered generations of innovation across ASIC and product development, spanning the breadth of the technology landscape. You’ll join a high-performance, globally connected engineering organization designing and delivering next-generation Digital and Mixed signal ASICs.

A sustained driver of Keysight’s success is the creation and deployment of breakthrough digital and mixed-signal ASICs that unlock step-function performance and customer value in new products. We are seeking an ASIC Physical Design R&D Manager to lead our ASIC Physical Design team—overseeing end-to-end physical implementation and ensuring designs meet aggressive performance, power, and area targets through tapeout and into product development.

The position is based in Colorado Springs at the foot of Pikes Peak, with a purpose-built development campus that brings engineering, advanced technology development, assembly, and machining together in one location. Outside the lab, the campus supports an active lifestyle with on-site fitness and recreation, and Colorado Springs offers exceptional quality of life—immediate access to world-class outdoor activities, year-round recreation, and more than 300 days of sunshine each year.


Responsibilities
  • Drive the physical design technical strategy across programs, including floorplanning, power architecture, and implementation trade-offs to meet PPA (performance, power, area) targets.
  • Lead, mentor, and grow a high-performing Physical Design team; set clear expectations for technical rigor, execution, and delivery.
  • Oversee physical implementation for digital, mixed-signal, and third-party IP—from block to subsystem to top-level integration—including place and route, timing closure, and power closure.
  • Coordinate closely with RTL/design, DFT/test, packaging, and systems teams to ensure clean handoffs, rapid issue resolution, and aligned delivery through tapeout.
  • Own and continuously improve the Physical Design flow, including methodology, automation, CI/regression infrastructure, and best-practice enablement for predictability and quality.
  • Lead physical verification and signoff (DRC/LVS, STA, power/IR/EM, reliability as applicable) and drive tape release readiness with clear signoff criteria.
  • Serve as the primary physical design interface to external CMOS/BiCMOS foundries and partners, ensuring alignment on PDKs, signoff requirements, and tapeout execution.
  • Own project execution across the physical design lifecycle—planning, resourcing, schedules, milestones, and risk mitigation—to deliver predictable tapeouts and product readiness.

Qualifications

Must-have Qualifications

  • B.S. or M.S. in Electrical Engineering or Computer Engineering (or equivalent experience).
  • 7+ years of relevant experience in digital ASIC physical design, including successful tape releases.
  • 5+ years of project/program management experience, including planning, dependency management, risk tracking, and cross-team execution to tapeout.

Preferred Qualifications

  • Demonstrated people leadership, including mentoring and coaching engineers, developing future technical leaders, and building an inclusive, high-accountability culture.
  • Expertise in physical implementation and layout methodology, including timing closure, signoff, and power/performance/area optimization.
  • Working knowledge of DFT methodologies (e.g., scan insertion/test considerations) and how they impact physical design, closure, and tape release.
  • Strong EE fundamentals with experience spanning ASIC design concepts, IP integration, and CMOS/BiCMOS processes.
  • Strong teamwork and problem-solving skills, with clear written and verbal communication across engineering and program stakeholders.
  • Leadership skills to drive change and influence cross-functional teams toward execution goals, quality, and predictable delivery.
  • Sound technical judgment under schedule pressure, with a track record of making effective PPA trade-offs while maintaining signoff quality.

ITAR statement: This position requires access to certain goods, software, technology, or technical data subject to U.S. export control laws and regulations. Under these laws and regulations, U.S. persons (which includes U.S. citizens, U.S. nationals, lawful permanent residents, refugees, and asylees) working for Keysight can access export-controlled items without authorization from the U.S. government. For any individual who is not a U.S. person, Keysight may need authorization from the U.S. Department of State, U.S. Department of Commerce, or other appropriate federal agency before the individual can access export-controlled items. Employment in this position for non-U.S. persons is contingent on Keysight’s ability to obtain any required government authorizations.

We are unable to support visa sponsorship for this position.

MIN $151,000.00 -   MAX $253,000.00

Most offers will be between the minimum and the midpoint of the Salary Range listed above.

#LI-MO1

Note: For other locations, pay ranges will vary by region

US Employees may be eligible for the following benefits:

  • Medical, dental and vision
  • Health Savings Account
  • Health Care and Dependent Care Flexible Spending Accounts
  • Life, Accident, Disability insurance
  • Business Travel Accident and Business Travel Health
  • 401(k) Plan
  • Flexible Time Off, Paid Holidays
  • Paid Family Leave
  • Discounts, Perks
  • Tuition Reimbursement
  • Adoption Assistance
  • ESPP (Employee Stock Purchase Plan)

Careers Privacy Statement***Keysight is an Equal Opportunity Employer.***

Qualifications:

Must-have Qualifications

  • B.S. or M.S. in Electrical Engineering or Computer Engineering (or equivalent experience).
  • 7+ years of relevant experience in digital ASIC physical design, including successful tape releases.
  • 5+ years of project/program management experience, including planning, dependency management, risk tracking, and cross-team execution to tapeout.

Preferred Qualifications

  • Demonstrated people leadership, including mentoring and coaching engineers, developing future technical leaders, and building an inclusive, high-accountability culture.
  • Expertise in physical implementation and layout methodology, including timing closure, signoff, and power/performance/area optimization.
  • Working knowledge of DFT methodologies (e.g., scan insertion/test considerations) and how they impact physical design, closure, and tape release.
  • Strong EE fundamentals with experience spanning ASIC design concepts, IP integration, and CMOS/BiCMOS processes.
  • Strong teamwork and problem-solving skills, with clear written and verbal communication across engineering and program stakeholders.
  • Leadership skills to drive change and influence cross-functional teams toward execution goals, quality, and predictable delivery.
  • Sound technical judgment under schedule pressure, with a track record of making effective PPA trade-offs while maintaining signoff quality.

ITAR statement: This position requires access to certain goods, software, technology, or technical data subject to U.S. export control laws and regulations. Under these laws and regulations, U.S. persons (which includes U.S. citizens, U.S. nationals, lawful permanent residents, refugees, and asylees) working for Keysight can access export-controlled items without authorization from the U.S. government. For any individual who is not a U.S. person, Keysight may need authorization from the U.S. Department of State, U.S. Department of Commerce, or other appropriate federal agency before the individual can access export-controlled items. Employment in this position for non-U.S. persons is contingent on Keysight’s ability to obtain any required government authorizations.

We are unable to support visa sponsorship for this position.

MIN $151,000.00 -   MAX $253,000.00

Most offers will be between the minimum and the midpoint of the Salary Range listed above.

#LI-MO1

Note: For other locations, pay ranges will vary by region

US Employees may be eligible for the following benefits:

  • Medical, dental and vision
  • Health Savings Account
  • Health Care and Dependent Care Flexible Spending Accounts
  • Life, Accident, Disability insurance
  • Business Travel Accident and Business Travel Health
  • 401(k) Plan
  • Flexible Time Off, Paid Holidays
  • Paid Family Leave
  • Discounts, Perks
  • Tuition Reimbursement
  • Adoption Assistance
  • ESPP (Employee Stock Purchase Plan)

Careers Privacy Statement***Keysight is an Equal Opportunity Employer.***

Education:UNAVAILABLEEmployment Type: UNAVAILABLE

What Keysight Technologies employees say

Pay

Benefits

Hours and flexibility

Workplace

Get the full story on Breakroom