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Physical Design Manager Jobs (NOW HIRING)

Eridu AI

Physical Design Engineer

Saratoga, CA · On-site

$210K - $250K/yr

Define the Physical Assembly of SOC. involving all aspects of physical design functions such as P&R ... Recruiting agencies are expressly instructed not to contact hiring managers, employees, or ...

Apple

GPU Physical Verification Design Engineer

Austin, TX · On-site

$134.80K - $138.80K/yr

You will manage and resolve design and flow issues related to physical design, identify potential solutions and drive execution. You will need to communicate and drive the needs of Physical Design ...

TSMC

Physical Design Engineer (7452)

San Jose, CA · On-site

$155.70K - $160.30K/yr

Join our dynamic Test Chip Physical Implementation team in San Jose, CA, and play a critical role ... management. * Extensive design optimization for power, performance, and area (PPA) targets.

TSMC

Physical Design Engineer (7452)

San Jose, CA · On-site

$155.70K - $160.30K/yr

Join our dynamic Test Chip Physical Implementation team in San Jose, CA, and play a critical role ... management. * Extensive design optimization for power, performance, and area (PPA) targets.

K2 Space

OR

$190K - $280K/yr

This role also involves managing external physical design partners, driving tool and flow decisions, and ensuring first-pass silicon success in advanced FinFET technologies. You'll be a key ...

Cerebras Systems

3D Physical Design Engineer

Sunnyvale, CA · On-site

$150K - $270K/yr

... managing hundreds of GPUs or TPUs. Cerebras' current customers include top model labs, global ... About The Role As a member of our tight knit physical design team, you will be working on the ...

Apple

GPU Physical Design Engineer

Austin, TX · On-site

$134.80K - $138.80K/yr

This role requires a mix of strategic engineering along with hands-on experience in physical design ... and thermal Management.Proven track record in solving complex PD and cross functional problems ...

trimarkusa

Design Manager

Lenexa, KS · On-site +1

The Manager, Design reports to the Regional Director, Design * Can be located in any of the ... description and physical requirements * Conduct site visits and punch lists per customer ...

Apple

GPU Physical Verification Design Engineer

Austin, TX · On-site

$181.10K - $318.40K/yr

You will manage and resolve design and flow issues related to physical design, identify potential solutions and drive execution. You will need to communicate and drive the needs of Physical Design ...

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How much do physical design manager jobs pay per year?

As of Jun 2, 2026, the average yearly pay for physical design manager in the United States is $114,491.00, according to ZipRecruiter salary data. Most workers in this role earn between $83,500.00 and $144,000.00 per year, depending on experience, location, and employer.

What is a Physical Design Manager job?

A Physical Design Manager oversees the physical implementation of integrated circuits (ICs), ensuring efficient design, timing closure, and power optimization. They lead a team of engineers responsible for tasks like floorplanning, place and route, clock tree synthesis, and signoff verification. Their role involves collaborating with design, verification, and manufacturing teams to meet project deadlines and performance targets. Strong technical expertise in EDA tools, process nodes, and industry standards is essential.

What are the key skills and qualifications needed to thrive in the Physical Design Manager position, and why are they important?

To thrive as a Physical Design Manager, you need a deep understanding of ASIC/SoC design flows, timing closure, floorplanning, and digital circuit fundamentals, often backed by a degree in electrical or computer engineering. Familiarity with EDA tools such as Cadence, Synopsys, or Mentor Graphics, and knowledge of industry standards like IEEE are crucial, while certifications in VLSI design can be advantageous. Strong leadership, project management abilities, and effective communication skills help in leading multidisciplinary teams and coordinating complex projects. These competencies ensure high-quality chip design delivery, efficient team performance, and on-time project completion in a fast-paced semiconductor environment.

What are some common challenges faced by Physical Design Managers, and how can they be addressed?

Physical Design Managers often encounter challenges such as managing tight project deadlines, achieving timing closure, and balancing trade-offs between power, performance, and area in chip designs. Coordination between multiple design teams and keeping up with evolving EDA tool technologies can also require effective communication and continuous learning. Proactive planning, strong technical mentorship, and fostering collaboration across teams help address these challenges. Staying up to date with industry advancements and encouraging a culture of open problem-solving are also key to overcoming common obstacles in this role.
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Physical Design Manager jobs near you
Infographic showing various Physical Design Manager job openings in the United States as of May 2026, with employment types broken down into 100% Full Time. Highlights an 100% In-person job distribution, with an average salary of $114,491 per year, or $55 per hour.

Physical Design Engineer

Eridu AI

Saratoga, CA • On-site

$210K - $250K/yr

Full-time

Posted 15 days ago

Job description

About Eridu
Eridu is a Silicon Valley-based hardware startup pioneering infrastructure solutions that accelerate AI data centers to deliver Faster AI. Today's AI performance is frequently limited by communication bottlenecks. Eridu delivers multiple industry-first innovations across silicon, packaging, software, and systems to deliver a step function in AI networking - a network switch that is an order of magnitude improvement in bandwidth and radix versus today's "state of the art" switches. This is the first silicon and system designed from the ground up for AI and the increase in radix and throughput unlocks greater GPU utilization to speed training job completion times and tokens-per-second for more profitable inference. We do this while simultaneously reducing capital and power costs, improving reliability, simplifying operations and speeding AI data center deployments for faster time to revenue.
The company's solutions and value proposition have been widely validated by leading hyperscalers.
The company has raised $200M to date including its most recent, oversubscribed Series A round led by Socratic Partners, John Doerr, Hudson River Trading, Capricorn Investment Group and Matter Venture Partners, with participation by SBVA, MediaTek, Bosch Ventures, TDK Ventures, Eclipse Ventures, and VentureTech Alliance, among others.
Eridu is led by a veteran team of Silicon Valley executives who have delivered multiple billion dollar product lines and led multiple companies to billion dollar exists, including serial entrepreneur Drew Perkins, co-founder of Infinera (NASDAQ: INFN), Lightera (acq. by Ciena), Gainspeed (acq. by Nokia) and Mojo Vision (the world's leading micro-LED company). The company is in execution mode and has a world-class engineering team with decades of experience in state-of-the-art silicon, packaging, optics, software, and systems. Eridu has also assembled a world class IP, design and manufacturing ecosystem to execute on its vision, and counts TSMC as a key partner in our journey.
Visit our website eridu.ai to learn more.
Key Responsibilities:
  • Define the Physical Assembly of SOC. involving all aspects of physical design functions such as P&R, timing, floorplan, clocking, electrical analysis, and power.
  • Proficiency in Synthesis design constraints (SDC).
  • Design and Architect Top Level and block Level Floor planning of the entire SoC.
  • Sound Proficiency in either Innovus or Synopsys Fusion Compiler required. Proficiency in synthesis, Floor planning Power Planning and Timing closure are required.
  • Prior experience with large skew optimized clock tree designs like H-Tree preferred. Clock Grid exposure is a plus.
  • Work extensively with Micro-architects to perform feasibility studies and explore performance, power & area (PPA) tradeoffs for design closure.
  • Develop physical design methodologies and customize recipes across various implementation steps to optimize PPA.
  • Work with a multi-functional engineering team to implement and validate physical design by running all signoff flows such as Timing, Power, EM/IR, PDV.

Qualifications
  • Master's Degree or bachelor's degree in EE with a minimum of 10+ years of experience.
  • Knowledge using synthesis, place & route, analysis and verification CAD tools.
  • Familiarity with logic & physical design principles to drive low-power & higher-performance designs.
  • Fluency in scripting in some of these languages: Unix, Perl, Python, and TCL.
  • Good understanding of device physics and experience in deep sub-micron technologies 7nm or below.
  • Knowledge of Verilog and System Verilog.
  • Excellent skills in problem solving, written and verbal communication, excellent organization skills, and highly self-motivated.
  • Ability to work well in a team and be productive under aggressive schedules.
  • Prior experience of multiple tape-out in deep submicron 7nm or below is required.

Why Join Us?
At Eridu, you'll have the opportunity to shape the future of AI infrastructure, working with a world-class team on groundbreaking technology that pushes the boundaries of AI performance. Your contributions will directly impact the next generation of AI infrastructure solutions, transforming the performance of AI data centers.
The starting base salary for the selected candidate will be established based on their relevant skills, experience, qualifications, work location, market trends, and the compensation of employees in comparable roles.
Notice to Recruiting Agencies
Eridu does not accept unsolicited resumes or candidate profiles from staffing agencies or third-party recruiters. Any candidate submitted to Eridu without prior written authorization from our recruiting team will be considered unsolicited and will become the property of Eridu. Eridu reserves the right to pursue and hire such candidates without any obligation to pay fees. Recruiting agencies are expressly instructed not to contact hiring managers, employees, or executives regarding open positions.
The pay range for this role is:
210,000 - 250,000 USD per year (San Francisco Bay Area)

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