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Physical Design Manager Jobs in California (NOW HIRING)

iFlow Inc

Physical Design Engineer

Sunnyvale, CA · On-site

$159K - $164K/yr

Top-Level Physical Design: • Chip-Level Floorplanning & Hierarchical Design - Manage top-level layout planning, pin assignments, and cross-block optimizations. • Strong scripting experience. • ...

Mirafra Technology

Physical Design Engineer

San Diego, CA

$144K - $148K/yr

We are 500+ employees in India and 250+ In US Clear visibility to senior management which helps for constant professional growth Title : Physical Design Engineer Location : San Diego,CA Type ...

Eridu AI

Physical Design Engineer

Saratoga, CA · On-site

$210K - $250K/yr

Define the Physical Assembly of SOC. involving all aspects of physical design functions such as P&R ... Recruiting agencies are expressly instructed not to contact hiring managers, employees, or ...

TSMC

Physical Design Engineer (7452)

San Jose, CA

$155K - $160K/yr

Join our dynamic Test Chip Physical Implementation team in San Jose, CA, and play a critical role ... management. * Extensive design optimization for power, performance, and area (PPA) targets.

TSMC

Physical Design Engineer (7452)

San Jose, CA · On-site

$155K - $160K/yr

Join our dynamic Test Chip Physical Implementation team in San Jose, CA, and play a critical role ... management. * Extensive design optimization for power, performance, and area (PPA) targets.

Cisco

Physical Design Engineer

San Jose, CA · On-site

$165K - $241K/yr

Your Impact As a Physical Design Engineer, you will play a key role in the full RTL-to-GDSII ... Implement and manage timing ECO strategies using tools like Tweaker/PrimeTime. * Analyze quality ...

Cisco

Physical Design Engineer

San Jose, CA · On-site

$165K - $241K/yr

Your Impact As a Physical Design Engineer, you will play a key role in the full RTL-to-GDSII ... Implement and manage timing ECO strategies using tools like Tweaker/PrimeTime. * Analyze quality ...

Cisco

Physical Design Engineer

San Jose, CA

$165K - $241K/yr

Your Impact As a Physical Design Engineer, you will play a key role in the full RTL-to-GDSII ... Implement and manage timing ECO strategies using tools like Tweaker/PrimeTime. * Analyze quality ...

Cisco

Physical Design Engineer

San Jose, CA · On-site

$165K - $241K/yr

Your Impact As a Physical Design Engineer, you will play a key role in the full RTL-to-GDSII ... Implement and manage timing ECO strategies using tools like Tweaker/PrimeTime. * Analyze quality ...

Insilico

Physical Design Engineer

San Jose, CA · On-site

$159K - $164K/yr

The management and its entire team, handpicked from among the best talents in the industry, can ... Job Title: Physical Design Engineer Location: San Jose, CA Experience: 5- 8 Years Duration: 12 ...

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Physical Design Manager information

See California salary details

$41.5K

$113K

$198.9K

How much do physical design manager jobs pay per year?

As of Jul 28, 2026, the average yearly pay for physical design manager in California is $112,992.00, according to ZipRecruiter salary data. Most workers in this role earn between $82,400.00 and $142,100.00 per year, depending on experience, location, and employer.

What are some common challenges faced by Physical Design Managers, and how can they be addressed?

Physical Design Managers often encounter challenges such as managing tight project deadlines, achieving timing closure, and balancing trade-offs between power, performance, and area in chip designs. Coordination between multiple design teams and keeping up with evolving EDA tool technologies can also require effective communication and continuous learning. Proactive planning, strong technical mentorship, and fostering collaboration across teams help address these challenges. Staying up to date with industry advancements and encouraging a culture of open problem-solving are also key to overcoming common obstacles in this role.

What is a Physical Design Manager job?

A Physical Design Manager oversees the physical implementation of integrated circuits (ICs), ensuring efficient design, timing closure, and power optimization. They lead a team of engineers responsible for tasks like floorplanning, place and route, clock tree synthesis, and signoff verification. Their role involves collaborating with design, verification, and manufacturing teams to meet project deadlines and performance targets. Strong technical expertise in EDA tools, process nodes, and industry standards is essential.

What are the key skills and qualifications needed to thrive in the Physical Design Manager position, and why are they important?

To thrive as a Physical Design Manager, you need a deep understanding of ASIC/SoC design flows, timing closure, floorplanning, and digital circuit fundamentals, often backed by a degree in electrical or computer engineering. Familiarity with EDA tools such as Cadence, Synopsys, or Mentor Graphics, and knowledge of industry standards like IEEE are crucial, while certifications in VLSI design can be advantageous. Strong leadership, project management abilities, and effective communication skills help in leading multidisciplinary teams and coordinating complex projects. These competencies ensure high-quality chip design delivery, efficient team performance, and on-time project completion in a fast-paced semiconductor environment.

What are popular job titles related to Physical Design Manager jobs in California? For Physical Design Manager jobs in California, the most frequently searched job titles are:
What job categories do people searching Physical Design Manager jobs in California look for? The top searched job categories for Physical Design Manager jobs in California are:
What cities in California are hiring for Physical Design Manager jobs? Cities in California with the most Physical Design Manager job openings:
Physical Design Manager jobs near you
Infographic showing various Physical Design Manager job openings in California as of July 2026, with employment types broken down into 87% Full Time, 10% Part Time, and 3% Contract. Highlights an 87% Physical, 4% Hybrid, and 9% Remote job distribution, with an average salary of $112,992 per year, or $54.3 per hour.
Physical Design Engineer

Physical Design Engineer

iFlow Inc

Sunnyvale, CA • On-site

$159K - $164K/yr

Contractor

Posted 29 days ago

Job description


Job Title: Physical Design Engineer 
Location:Sunnyvale, CA OR Austin,TX
Duration: Long term
experience: 5–18 years only (No 18+ years profile)

Job Overview:
We are looking for a highly skilled Physical Design Engineer to work at block level and/or top level for high-performance ASICs, SoCs, and custom silicon chips with strong scripting skills. The ideal candidate will be responsible for various aspects of the backend VLSI design flow, including floorplanning, placement, clock tree synthesis (CTS), routing, timing closure, and sign-off verification. The role requires expertise in EDA tools, physical verification methodologies, power optimization, and performance tuning.
Key Responsibilities:
Block-Level Physical Design:
• Floorplanning & Partitioning – Define optimal floorplan with power grid, macro placements, and congestion analysis.
• Strong scripting experience.
• Placement & Optimization – Perform standard cell placement, legalization, and optimization to improve area, power, and timing.
• Clock Tree Synthesis (CTS) – Design and optimize low-skew, high-performance clock networks.
• Routing & DRC Closure – Ensure successful global and detailed routing, meeting design rule constraints.
• Timing Closure – Work on setup/hold timing violations, signal integrity, and cross-talk reduction using static timing analysis (STA).
• Power & IR Drop Analysis – Optimize power planning, power integrity (IR drop, EM), and leakage reduction techniques.
Top-Level Physical Design:
• Chip-Level Floorplanning & Hierarchical Design – Manage top-level layout planning, pin assignments, and cross-block optimizations.
• Strong scripting experience.
• Clock & Power Distribution – Design robust clock trees and power delivery networks (PDN).
• Integration of IP & Sub-blocks – Ensure seamless integration of IP blocks and handle complex routing challenges.
• Chip Assembly & Sign-Off – Perform final netlist-to-GDSII implementation, addressing physical and electrical verification.
• DFT Integration – Work with Design for Test (DFT) teams to ensure scan chain connectivity and testability.
 
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