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Physical Design Manager Jobs in California (NOW HIRING)

Carman Solutions Group

Physical Design Manager

San Jose, CA · On-site

$159K - $164K/yr

Position Overview We are seeking a seasoned Physical Design Manager to lead advanced SoC physical implementation activities and drive designs through timing and signoff closure. The ideal candidate ...

Quest Global

Physical Design Manager

Santa Clara, CA · On-site

$158K - $163K/yr

Role - Physical Design Manager Location - Santa Clara, CA, USA Work Experience What You will Do: * Drive physical design flow: synthesis, floorplanning, placement, CTS, routing, timing closure.

iFlow Inc

Physical Design Engineer

Sunnyvale, CA · On-site

$159K - $164K/yr

Chip-Level Floorplanning & Hierarchical Design - Manage top-level layout planning, pin assignments, and cross-block optimizations. * Strong scripting experience. * Clock & Power Distribution - Design ...

Conductor

Physical Design Engineer

San Francisco, CA · On-site

$160K - $164K/yr

We're looking for physical design engineers to help manage and execute the physical design process for the various dies that comprise our A-0 and A-1 systems. This will involve deciding what to do in ...

Apple

ASIC Design Manager

Cupertino, CA · On-site

... Physical Design teams - Collaborate with software and systems teams to ensure a high quality ... Experience Managing a team and being a technical lead Experience writing specifications and ...

Mirafra Technology

Physical Design Engineer

San Diego, CA · On-site

$144K - $148K/yr

We are 500+ employees in India and 250+ In US Clear visibility to senior management which helps for constant professional growth Title : Physical Design Engineer Location : San Diego,CA Type ...

Broadcom

Physical Design Engineer

San Jose, CA · On-site

$159K - $164K/yr

... and managing mega datacenters, while leading world class performance, through our Enterprise ... Execution of Physical Design, Synthesis, Physical Verification, and Timing Closure * Setup and ...

Eridu Corporation

Physical Design Engineer

Saratoga, CA · On-site

$150K - $154K/yr

Involving all aspects of physical design functions such as P&R, timing, floorplan, clocking ... Recruiting agencies are expressly instructed not to contact hiring managers, employees, or ...

Broadcom

Physical Design Engineer

San Jose, CA · On-site

$159K - $164K/yr

... and managing mega datacenters, while leading world class performance, through our Enterprise ... Execution of Physical Design, Synthesis, Physical Verification, and Timing Closure * Setup and ...

Broadcom

Physical Design Engineer

San Jose, CA · On-site

$159K - $164K/yr

... and managing mega datacenters, while leading world class performance, through our Enterprise ... Execution of Physical Design, Synthesis, Physical Verification, and Timing Closure * Setup and ...

Altera

Senior Physical Design Engineer

San Jose, CA · On-site

$133K - $192K/yr

Perform physical design implementation of custom IP and SoC designs from RTL through GDSII to ... Ability to manage multiple technical priorities in a fast-paced development environment. * Passion ...

Socket.dev

Senior Physical Design Engineer

San Jose, CA · On-site

$133K - $192K/yr

Perform physical design implementation of custom IP and SoC designs from RTL through GDSII to ... Ability to manage multiple technical priorities in a fast‑paced development environment.

Eridu AI

Physical Design Engineer

Saratoga, CA · On-site

$210K - $250K/yr

Define the Physical Assembly of SOC. involving all aspects of physical design functions such as P&R ... Recruiting agencies are expressly instructed not to contact hiring managers, employees, or ...

Nutanix

Physical Design (Multiple levels)

San Diego, CA · On-site

$144K - $148K/yr

Qualcomm is seeking talented Physical Design Engineers to join our growing SoC and ASIC Design ... DFT-aware physical implementation and constraint management.Programming and automation using Python ...

Qualcomm

Physical Design (Multiple levels)

San Diego, CA · On-site

$144K - $148K/yr

Qualcomm is seeking talented Physical Design Engineers to join our growing SoC and ASIC Design ... DFT-aware physical implementation and constraint management. * Programming and automation using ...

Apple

ASIC Design Manager

Cupertino, CA · On-site

$206K - $356K/yr

... and Physical Design teams - Collaborate with software and systems teams to ensure a high quality product Preferred Qualifications Experience Managing a team and being a technical lead Experience ...

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Physical Design Manager information

See California salary details

$41.5K

$113K

$198.9K

How much do physical design manager jobs pay per year?

As of Sep 12, 2026, the average yearly pay for physical design manager in California is $112,992.00, according to ZipRecruiter salary data. Most workers in this role earn between $82,400.00 and $142,100.00 per year, depending on experience, location, and employer.

What is a physical design manager?

A Physical Design Manager oversees the physical implementation of integrated circuits (ICs), ensuring efficient design, timing closure, and power optimization. They lead a team of engineers responsible for tasks like floorplanning, place and route, clock tree synthesis, and signoff verification. Their role involves collaborating with design, verification, and manufacturing teams to meet project deadlines and performance targets. Strong technical expertise in EDA tools, process nodes, and industry standards is essential.

What are some common challenges faced by physical design managers, and how can they be addressed?

Physical Design Managers often encounter challenges such as managing tight project deadlines, achieving timing closure, and balancing trade-offs between power, performance, and area in chip designs. Coordination between multiple design teams and keeping up with evolving EDA tool technologies can also require effective communication and continuous learning. Proactive planning, strong technical mentorship, and fostering collaboration across teams help address these challenges. Staying up to date with industry advancements and encouraging a culture of open problem-solving are also key to overcoming common obstacles in this role.

What are the key skills and qualifications needed to thrive as a physical design manager, and why are they important?

To thrive as a Physical Design Manager, you need a deep understanding of ASIC/SoC design flows, timing closure, floorplanning, and digital circuit fundamentals, often backed by a degree in electrical or computer engineering. Familiarity with EDA tools such as Cadence, Synopsys, or Mentor Graphics, and knowledge of industry standards like IEEE are crucial, while certifications in VLSI design can be advantageous. Strong leadership, project management abilities, and effective communication skills help in leading multidisciplinary teams and coordinating complex projects. These competencies ensure high-quality chip design delivery, efficient team performance, and on-time project completion in a fast-paced semiconductor environment.

What are the most commonly searched types of Physical Design jobs in California?

The most popular types of Physical Design jobs in California are:

What are popular job titles related to Physical Design Manager jobs in California?

For Physical Design Manager jobs in California, the most frequently searched job titles are:

What job categories do people searching Physical Design Manager jobs in California look for?

The top searched job categories for Physical Design Manager jobs in California are:

What cities in California are hiring for Physical Design Manager jobs?

Cities in California with the most Physical Design Manager job openings:

Physical Design Manager jobs near you
Infographic showing various Physical Design Manager job openings in California as of September 2026, with employment types broken down into 2% As Needed, 73% Full Time, 20% Part Time, 1% Temporary, 3% Contract, and 1% Nights. Highlights an 95% Physical, 1% Hybrid, and 4% Remote job distribution, with an average salary of $112,992 per year, or $54.3 per hour.

Physical Design Manager

San Jose, CA • On-site

Carman Solutions Group
51 - 200 employees
Learn more about Carman Solutions Groupexternal

$159K - $164K/yr

Other

Posted 16 days ago

Job description

Position Overview

We are seeking a seasoned Physical Design Manager to lead advanced SoC physical implementation activities and drive designs through timing and signoff closure. The ideal candidate will bring extensive experience with RTL-to-GDSII execution, advanced process technologies, low-power methodologies, physical design automation, and cross-functional technical leadership.

Key Responsibilities
  • Lead the complete physical implementation flow, including synthesis, floorplan planning, placement, clock-tree synthesis, routing, optimization, and timing closure.
  • Drive implementation of power-efficient designs using advanced UPF techniques for 5nm/3nm and other leading-edge process nodes.
  • Troubleshoot complex SoC and subsystem integration issues, including SDC constraint management and UPF promotion, propagation, and pushdown.
  • Create, enhance, and support physical design automation and productivity flows using Tcl, Python, Perl, and Shell scripting.
  • Partner with RTL, STA, power, IP, and other engineering teams to resolve design issues and achieve physical and signoff closure.
  • Provide technical direction, mentorship, and guidance to junior engineers while helping build a strong physical design team.
  • Identify opportunities for improving design methodologies, implementation flows, automation, and overall engineering productivity.
  • Interface effectively with IP teams and EDA tool vendors to address technical challenges and improve design execution.
Required Qualifications
  • 10+ years of professional experience in physical design, physical implementation, and timing closure.
  • Bachelor’s degree in Computer Science, Computer Engineering, Electrical Engineering, or a related technical discipline, or equivalent practical experience.
  • Strong understanding of the RTL-to-GDSII flow, with experience contributing to or leading tape-outs on 5nm or smaller process technologies.
  • Hands-on proficiency with industry-standard EDA tools, including one or more of Synopsys Design Compiler (DC), Cadence Genus, Innovus, Synopsys ICC2, PrimeTime, RedHawk, Voltus, and Calibre.
  • Demonstrated experience in SoC floorplanning, placement and routing, clock-tree implementation, power distribution, and timing optimization for high-performance designs.
  • Good understanding of how process technology, physical geometry, and device characteristics influence physical design implementation and optimization.
  • Proven ability to work effectively with cross-functional engineering organizations, including IP, design, timing, and EDA vendor teams.
  • Strong interpersonal, communication, collaboration, and technical leadership skills.
  • Programming and automation experience with Tcl, Python, Perl, and/or Shell.

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