Principal ASIC Design Engineer Description: Expertise in at least 3 of the following: communication system design, RF radio design, digital ASIC design, applications platforms, and semiconductor ...
Principal ASIC Design Engineer Description: Expertise in at least 3 of the following: communication system design, RF radio design, digital ASIC design, applications platforms, and semiconductor ...
Principal ASIC Design Engineer
Carlsbad, CA · On-site
Principal ASIC Design Engineer Description: Expertise in at least 3 of the following: communication system design, RF radio design, digital ASIC design, applications platforms, and semiconductor ...
Principal ASIC Design Engineer
Carlsbad, CA · On-site
Principal ASIC Design Engineer Description: Expertise in at least 3 of the following: communication system design, RF radio design, digital ASIC design, applications platforms, and semiconductor ...
We are now looking for a Senior ASIC Design Engineer to join our System ASIC team! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 fueled the growth of ...
We are now looking for a Senior ASIC Design Engineer to join our System ASIC team! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 fueled the growth of ...
Senior ASIC Design Engineer
Santa Clara, CA · On-site
We are now looking for a Senior ASIC Design Engineer to join our System ASIC team! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 fueled the growth of ...
Senior ASIC Design Engineer
Santa Clara, CA · On-site
We are now looking for a Senior ASIC Design Engineer to join our System ASIC team! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 fueled the growth of ...
Senior ASIC Design Engineer with Security Clearance
Saratoga, CA · On-site
$250K - $290K/yr
Piper Companies is looking for a Senior ASIC Design Engineer to join a cutting-edge AI networking company onsite in Saratoga, CA Monday - Friday , to help define and build the next generation of high ...
Senior ASIC Design Engineer with Security Clearance
Saratoga, CA · On-site
$250K - $290K/yr
Piper Companies is looking for a Senior ASIC Design Engineer to join a cutting-edge AI networking company onsite in Saratoga, CA Monday - Friday , to help define and build the next generation of high ...
ASIC Design Engineer
Santa Clara, CA · On-site
$126K - $190K/yr
This role is hands-on and requires ownership of the design through the complete ASIC lifecycle , from concept through tape-out. The candidate will collaborate closely with other subsystem teams to ...
ASIC Design Engineer
Santa Clara, CA · On-site
$126K - $190K/yr
This role is hands-on and requires ownership of the design through the complete ASIC lifecycle , from concept through tape-out. The candidate will collaborate closely with other subsystem teams to ...
Senior Manager, ASIC Design
Santa Clara, CA · On-site
What You Can Expect We are seeking an experienced Senior Manager, ASIC Design to lead our ASIC chip design team. Reporting to the Senior Director, ASIC Engineering, you will manage a team and oversee ...
Senior Manager, ASIC Design
Santa Clara, CA · On-site
What You Can Expect We are seeking an experienced Senior Manager, ASIC Design to lead our ASIC chip design team. Reporting to the Senior Director, ASIC Engineering, you will manage a team and oversee ...
The Mixed-Signal IP team at Qualcomm is seeking skilled RTL and ASIC design engineers to contribute to the development of next-generation Mixed-Signal IPs - including DAC, ADC, and PLLs - for ...
The Mixed-Signal IP team at Qualcomm is seeking skilled RTL and ASIC design engineers to contribute to the development of next-generation Mixed-Signal IPs - including DAC, ADC, and PLLs - for ...
Senior ASIC Design Engineer
Santa Clara, CA · On-site
NVIDIA is seeking ASIC Design Engineers to implement the world's leading SoC's and GPU's. This position offers the opportunity to have real impact in a multifaceted, technology-focused company ...
Senior ASIC Design Engineer
Santa Clara, CA · On-site
NVIDIA is seeking ASIC Design Engineers to implement the world's leading SoC's and GPU's. This position offers the opportunity to have real impact in a multifaceted, technology-focused company ...
Experience and understanding of ASIC design flow: Architecture, Microarchitecture, verilog/system-verilog RTL design, Clock Domain Crossings, DFT, synthesis, and timing closure * Knowledge of bus ...
Experience and understanding of ASIC design flow: Architecture, Microarchitecture, verilog/system-verilog RTL design, Clock Domain Crossings, DFT, synthesis, and timing closure * Knowledge of bus ...
ASIC Design Engineer lll This role has been designed as ''Onsite' with an expectation that you will primarily work from an HPE office. Who We Are: Hewlett Packard Enterprise is the global edge-to ...
ASIC Design Engineer lll This role has been designed as ''Onsite' with an expectation that you will primarily work from an HPE office. Who We Are: Hewlett Packard Enterprise is the global edge-to ...
ASIC Design Engineer lll
Sunnyvale, CA · On-site
ASIC Design Engineer lll This role has been designed as ''Onsite' with an expectation that you will primarily work from an HPE office. Who We Are: Hewlett Packard Enterprise is the global edge-to ...
ASIC Design Engineer lll
Sunnyvale, CA · On-site
ASIC Design Engineer lll This role has been designed as ''Onsite' with an expectation that you will primarily work from an HPE office. Who We Are: Hewlett Packard Enterprise is the global edge-to ...
ASIC Design Engineer lll This role has been designed as ''Onsite' with an expectation that you will primarily work from an HPE office. Who We Are: Hewlett Packard Enterprise is the global edge-to ...
ASIC Design Engineer lll This role has been designed as ''Onsite' with an expectation that you will primarily work from an HPE office. Who We Are: Hewlett Packard Enterprise is the global edge-to ...
What You Can Expect We are seeking an experienced Senior Manager, ASIC Design to lead our ASIC chip design team. Reporting to the Senior Director, ASIC Engineering, you will manage a team and oversee ...
What You Can Expect We are seeking an experienced Senior Manager, ASIC Design to lead our ASIC chip design team. Reporting to the Senior Director, ASIC Engineering, you will manage a team and oversee ...
Sr. Engineer, ASIC Design
San Jose, CA · On-site
$160K - $192K/yr
Engineer, ASIC Design Location: San Jose (on-site) Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light ...
Sr. Engineer, ASIC Design
San Jose, CA · On-site
$160K - $192K/yr
Engineer, ASIC Design Location: San Jose (on-site) Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light ...
ASIC Design Engineer lll This role has been designed as ''Onsite' with an expectation that you will primarily work from an HPE office. Who We Are: Hewlett Packard Enterprise is the global edge-to ...
ASIC Design Engineer lll This role has been designed as ''Onsite' with an expectation that you will primarily work from an HPE office. Who We Are: Hewlett Packard Enterprise is the global edge-to ...
NVIDIA is seeking ASIC Design Engineers to implement the world's leading SoC's and GPU's. This position offers the opportunity to have real impact in a multifaceted, technology-focused company ...
NVIDIA is seeking ASIC Design Engineers to implement the world's leading SoC's and GPU's. This position offers the opportunity to have real impact in a multifaceted, technology-focused company ...
We are now looking for an ASIC Design Engineer. NVIDIA is seeking best-in-class ASIC Design Engineers to design and implement the world's leading SoC's and GPU's. This position offers the opportunity ...
We are now looking for an ASIC Design Engineer. NVIDIA is seeking best-in-class ASIC Design Engineers to design and implement the world's leading SoC's and GPU's. This position offers the opportunity ...
Senior Manager, ASIC Design Engineering
San Jose, CA · On-site +1
We're seeking engineers who are energized by working on cutting-edge ASIC design and distributed software systems, and who are motivated to push the boundaries on how AI can transform everything from ...
Senior Manager, ASIC Design Engineering
San Jose, CA · On-site +1
We're seeking engineers who are energized by working on cutting-edge ASIC design and distributed software systems, and who are motivated to push the boundaries on how AI can transform everything from ...
ASIC Design Engineer Responsibilities: * Define and bring up FPGA platforms for pre-silicon validation and software development * Map ASIC RTL to FGPA while minimizing code base differences * Create ...
Quick apply
ASIC Design Engineer Responsibilities: * Define and bring up FPGA platforms for pre-silicon validation and software development * Map ASIC RTL to FGPA while minimizing code base differences * Create ...
Asic Design information
See California salary details
$92.8K - $102.5K
16% of jobs
$102.5K - $112.1K
3% of jobs
$112.1K - $121.8K
4% of jobs
$124.7K is the 25th percentile. Wages below this are outliers.
$121.8K - $131.5K
6% of jobs
The median wage is $137.6K / yr.
$131.5K - $141.2K
33% of jobs
$141.2K - $150.9K
3% of jobs
$150.9K - $160.6K
2% of jobs
$167K is the 75th percentile. Wages above this are outliers.
$160.6K - $170.3K
12% of jobs
$170.3K - $180K
5% of jobs
$180K - $189.7K
4% of jobs
$189.7K - $199.4K
12% of jobs
$92.8K
$148.2K
$199.4K
How much do asic design jobs pay per year?
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What engineer makes $500,000 a year?
How much do ASIC designers make?
What are the key skills and qualifications needed to thrive as an ASIC Design Engineer, and why are they important?
What is the difference between Asic Design vs FPGA Design?
| Aspect | Asic Design | FPGA Design |
|---|---|---|
| Credentials | Bachelor's or Master's in Electrical Engineering or Computer Engineering; knowledge of VLSI design | Similar credentials; often requires knowledge of FPGA programming languages like VHDL/Verilog |
| Work Environment | Designing custom chips in semiconductor labs or design houses | Implementing and testing designs on FPGA boards in labs or development environments |
| Industry Usage | Used in high-volume, performance-critical applications like smartphones, servers | Used for prototyping, testing, and low to medium volume applications |
While both Asic Design and FPGA Design involve hardware description languages and digital logic, Asic Design focuses on creating custom chips for high-volume production, requiring detailed fabrication knowledge. FPGA Design emphasizes flexible, reprogrammable hardware for testing and prototyping. Understanding these differences helps professionals choose the right career path or project focus within the hardware design industry.
Is ASIC design in demand?
What are some common challenges faced by ASIC Design Engineers during the chip development process?
What are ASIC designers?

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Job description
Principal ASIC Design Engineer Description: Expertise in at least 3 of the following: communication system design, RF radio design, digital ASIC design, applications platforms, and semiconductor device modeling. Requirements: Principal Engineer will be responsible for design and development from multiple ASIC blocks to a complete Core/Chip in communications/digital signal processing (DSP) IC products. These include building blocks/Cores for communication functions.
The responsibility includes working with system engineering or product marketing department to close design specifications, define block/core/chip architectures, carry out and verify the design. Need to Have: Communications/DSP algorithm and efficient implementations. System-on-the-chip architectures Knowledge and hand-on experience from industry ASIC design flow including RTL coding, debugging/verification, synthesizing and supporting timing closure.
Design experience in Communications/DSP building blocks and/or SOC functional modules. Experience with design tools such as NCSIM (and/or VCS), Cadence RC or Synopsys DC compiler, Experience with multiple IC tape-out in industry. Experience in chip bring up and performance measurement for IC and systems in laboratory to characterize and debug building blocks MS in EE with 12 years of experience or Ph.D
in EE with 10 years of experience.