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Asic Design Manager Jobs in California (NOW HIRING)

What You Can Expect We are seeking an experienced Senior Manager, ASIC Design to lead our ASIC chip design team. Reporting to the Senior Director, ASIC Engineering, you will manage a team and oversee ...

Sr. Engineer, ASIC Design

San Jose, CA ยท On-site

$160K - $192K/yr

Engineer, ASIC Design Location: San Jose (on-site) Ayar Labs is shattering AI data bottlenecks by ... manage his or her own time to take projects to completion with limited supervision and guidance.

Sr. Engineer, ASIC Design

San Jose, CA ยท On-site

$160K - $192K/yr

Engineer, ASIC Design Location: San Jose (on-site) Ayar Labs is shattering AI data bottlenecks by ... manage his or her own time to take projects to completion with limited supervision and guidance.

Sr. Staff Engineer, ASIC Design

San Jose, CA ยท On-site

$180K - $223K/yr

Sr. Staff Engineer, ASIC Design Location: San Jose (on-site) Ayar Labs is shattering AI data ... manage his or her own time to take projects to completion with limited supervision and guidance.

ASIC Engineer

San Jose, CA

$194K/yr

With over 20 man years of contingent staffing experience, the management & execution team is ... ASIC Design, FPGA, RTL Design, Chip Architecture, ASIC, Implementation,Synthesis /Conformal ...

Sr. Staff Engineer, ASIC Design Location: San Jose (on-site) Ayar Labs is shattering AI data ... manage his or her own time to take projects to completion with limited supervision and guidance.

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Showing results 1-20

Asic Design Manager information

See California salary details

$41.5K

$113K

$198.9K

How much do asic design manager jobs pay per year?

As of Jul 27, 2026, the average yearly pay for asic design manager in California is $112,992.00, according to ZipRecruiter salary data. Most workers in this role earn between $82,400.00 and $142,100.00 per year, depending on experience, location, and employer.

What is the difference between Asic Design Manager vs Asic Design Engineer?

AspectAsic Design ManagerAsic Design Engineer
ResponsibilitiesOversees ASIC design projects, manages teams, and coordinates with stakeholdersPerforms ASIC design, coding, simulation, and verification tasks
Required SkillsLeadership, project management, ASIC design knowledgeHardware description languages, circuit design, verification skills
ExperienceTypically 8+ years in ASIC design, with leadership experienceUsually 2-5 years in ASIC design roles
Work EnvironmentDesign teams, project planning, cross-functional collaborationDesign labs, simulation environments, coding and testing

The main difference between an Asic Design Manager and an Asic Design Engineer lies in their roles. The manager oversees projects and teams, focusing on leadership and coordination, while the engineer concentrates on technical ASIC design and implementation. Both roles require ASIC design expertise, but the manager's role is more strategic and supervisory.

What are the key skills and qualifications needed to thrive as an ASIC Design Manager, and why are they important?

To thrive as an ASIC Design Manager, you need expertise in digital and analog ASIC design, project management experience, and typically a degree in electrical engineering or a related field. Familiarity with industry-standard EDA tools (such as Cadence or Synopsys), verification methodologies, and knowledge of relevant design flows is crucial. Strong leadership, communication, and problem-solving skills help manage teams and coordinate with cross-functional stakeholders. These competencies ensure high-quality chip designs are delivered on time and meet performance and cost targets, which is vital for organizational success.

What are some common challenges faced by an ASIC Design Manager in leading multidisciplinary teams?

ASIC Design Managers often navigate the complexities of coordinating multidisciplinary teams, including digital, analog, verification, and physical design engineers. One common challenge is ensuring clear communication across these specialties to maintain alignment on project goals, timelines, and technical requirements. Additionally, managing shifting priorities, resolving technical bottlenecks, and balancing resource allocation are frequent hurdles. Successful managers foster collaboration, set clear expectations, and leverage structured project management practices to keep teams productive and motivated.

What does an ASIC Design Manager do?

An ASIC Design Manager oversees the design and development of Application Specific Integrated Circuits (ASICs), managing a team of engineers through the entire chip design process. They coordinate project timelines, ensure technical specifications are met, and facilitate communication between design, verification, and manufacturing teams. Their role also involves resource planning, risk management, and ensuring that the final product meets performance, cost, and quality targets.
What are the most commonly searched types of Asic Design jobs in California? The most popular types of Asic Design jobs in California are:
What are popular job titles related to Asic Design Manager jobs in California? For Asic Design Manager jobs in California, the most frequently searched job titles are:
What job categories do people searching Asic Design Manager jobs in California look for? The top searched job categories for Asic Design Manager jobs in California are:
What cities in California are hiring for Asic Design Manager jobs? Cities in California with the most Asic Design Manager job openings:
Infographic showing various Asic Design Manager job openings in California as of July 2026, with employment types broken down into 91% Full Time, 4% Part Time, 1% Temporary, 2% Contract, and 2% Summer. Highlights an 89% Physical, 6% Hybrid, and 5% Remote job distribution, with an average salary of $112,992 per year, or $54.3 per hour.
Senior Manager, ASIC Design

Senior Manager, ASIC Design

Marvell Technology, Inc.

Santa Clara, CA โ€ข On-site

Full-time

Life, Retirement

Posted 11 days ago


Job description

About Marvell
Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
As Generative AI continues to advance, the performance drivers for data center infrastructure are shifting from systems-on-chip (SOCs) to systems of chips. In the era of Accelerated Computing, data center bottlenecks are no longer limited to compute performance, but rather the system's interconnect bandwidth, memory bandwidth, and memory capacity. Celestial AI's Photonic Fabricโ„ข is the next-generation interconnect technology that delivers a tenfold increase in performance and energy efficiency compared to competing solutions.
The Photonic Fabricโ„ข is available to our customers in multiple technology offerings, including optical interface chiplets, optical interposers, and Optical Multi-chip Interconnect Bridges (OMIB). This allows customers to easily incorporate high bandwidth, low power, and low latency optical interfaces into their AI accelerators and GPUs. The technology is fully compatible with both protocol and physical layers, including standard 2.5D packaging processes. This seamless integration enables XPUs to utilize optical interconnects for both compute-to-compute and compute-to-memory fabrics, achieving bandwidths in the tens of terabits per second with nanosecond latencies.
This innovation empowers hyperscalers to enhance the efficiency and cost-effectiveness of AI processing by optimizing the XPUs required for training and inference, while significantly reducing the TCO2 impact. To bolster customer collaborations, Celestial AI is developing a Photonic Fabric ecosystem consisting of tier-1 partnerships that include custom silicon/ASIC design, system integrators, HBM memory, assembly, and packaging suppliers.
What You Can Expect
We are seeking an experienced Senior Manager, ASIC Design to lead our ASIC chip design team. Reporting to the Senior Director, ASIC Engineering, you will manage a team and oversee the end-to-end design and development of high-performance ASICs, ensuring technical excellence, on-time project delivery, and alignment with company goals.
This role demands proven technical expertise in advanced ASIC design flows and leadership in execution, scheduling, cross-functional coordination, and final product delivery.
What We're Looking For
  • Bachelor's degree in Computer Science, Electrical Engineering or related fields and 5-10 years of related professional experience or Master's degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-5 years of experience or equivalent professional experience in lieu of a formal degree
  • 8+ years of ASIC/SOC digital design experience
  • 3+ years of people management experience
  • Excellent leadership, communication, team building and stakeholder management skills
  • Ability to coordinate across multiple projects, manage risks and escalations, and work under tight schedules and budget constraints
  • Strong knowledge across the full ASIC/SOC development cycle from microarchitecture development to tape-out in advanced process technologies
  • Outstanding technical expertise in microarchitecture development, RTL coding (Verilog/SystemVerilog), synthesis, STA/timing closure, physical design, and verification methodologies
  • Hands on design experience in one or more industry standards/protocol stacks such as CXL, PCIe, HBM, UCIe, UALink etc
  • Demonstrated ability to optimize designs for PPA (power, performance, area) and to integrate major subsystems (interconnect, I/O, memory)
  • Proficiency with front end development tools/methodologies, and scripting for automation and flow integration

Expected Base Pay Range (USD)
161,600 - 239,210, $ per annum
The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements
Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life's most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.
Interview Integrity
To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.
This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.
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