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Asic Design Manager Jobs in California (NOW HIRING)

Meta

ASIC Engineer, Design Verification

Sunnyvale, CA · On-site +1

$114K/yr

Meta is hiring an ASIC Design Verification Engineer within the Infrastructure Silicon organization ... management * Participate in design reviews and verification planning discussions to identify ...

Meta

ASIC Engineer, EDA Infrastructure

Sunnyvale, CA

$114K/yr

Work with internal infrastructure team on adapting internal infrastructure to ASIC design solutions, including but not limited to Source Control Management, Continuous Integration, data management ...

Meta

ASIC Engineer, EDA Infrastructure

Menlo Park, CA

$114K/yr

Work with internal infrastructure team on adapting internal infrastructure to ASIC design solutions, including but not limited to Source Control Management, Continuous Integration, data management ...

Broadcom

ASIC Package Design Manager

San Jose, CA

Self-management and organization skills * Technical understanding related to package design: * Package-Design lifecycle * How the substrate and package fit into the overall ASIC design and ...

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All JobsAsic Design JobsAsic Design Manager JobsAsic Design Manager Jobs in California

Asic Design Manager information

See California salary details

$41.5K

$113K

$198.9K

How much do asic design manager jobs pay per year?

As of Aug 8, 2026, the average yearly pay for asic design manager in California is $112,992.00, according to ZipRecruiter salary data. Most workers in this role earn between $82,400.00 and $142,100.00 per year, depending on experience, location, and employer.

Is ASIC design in demand?

ASIC design is in high demand due to the growth of industries such as consumer electronics, telecommunications, and automotive technology. Skilled ASIC design managers with expertise in hardware description languages and verification tools are sought after to develop custom integrated circuits for various applications.

What is the difference between Asic Design Manager vs Asic Design Engineer?

AspectAsic Design ManagerAsic Design Engineer
ResponsibilitiesOversees ASIC design projects, manages teams, and coordinates with stakeholdersPerforms ASIC design, coding, simulation, and verification tasks
Required SkillsLeadership, project management, ASIC design knowledgeHardware description languages, circuit design, verification skills
ExperienceTypically 8+ years in ASIC design, with leadership experienceUsually 2-5 years in ASIC design roles
Work EnvironmentDesign teams, project planning, cross-functional collaborationDesign labs, simulation environments, coding and testing

The main difference between an Asic Design Manager and an Asic Design Engineer lies in their roles. The manager oversees projects and teams, focusing on leadership and coordination, while the engineer concentrates on technical ASIC design and implementation. Both roles require ASIC design expertise, but the manager's role is more strategic and supervisory.

What are the key skills and qualifications needed to thrive as an ASIC Design Manager?

To thrive as an ASIC Design Manager, you need expertise in digital and analog ASIC design, project management experience, and typically a degree in electrical engineering or a related field. Familiarity with industry-standard EDA tools (such as Cadence or Synopsys), verification methodologies, and knowledge of relevant design flows is crucial. Strong leadership, communication, and problem-solving skills help manage teams and coordinate with cross-functional stakeholders. These competencies ensure high-quality chip designs are delivered on time and meet performance and cost targets, which is vital for organizational success.

Is ASIC design difficult?

ASIC design is a complex process that requires strong knowledge of digital logic, hardware description languages like VHDL or Verilog, and familiarity with electronic design automation tools. It involves multiple stages such as architecture, verification, and testing, making it challenging but manageable with proper training and experience.

What are some common challenges faced by an ASIC Design Manager in leading multidisciplinary teams?

ASIC Design Managers often navigate the complexities of coordinating multidisciplinary teams, including digital, analog, verification, and physical design engineers. One common challenge is ensuring clear communication across these specialties to maintain alignment on project goals, timelines, and technical requirements. Additionally, managing shifting priorities, resolving technical bottlenecks, and balancing resource allocation are frequent hurdles. Successful managers foster collaboration, set clear expectations, and leverage structured project management practices to keep teams productive and motivated.

What does an ASIC Design Manager do?

An ASIC Design Manager oversees the design and development of Application Specific Integrated Circuits (ASICs), managing a team of engineers through the entire chip design process. They coordinate project timelines, ensure technical specifications are met, and facilitate communication between design, verification, and manufacturing teams. Their role also involves resource planning, risk management, and ensuring that the final product meets performance, cost, and quality targets.
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Asic Design Manager jobs near you
Infographic showing various Asic Design Manager job openings in California as of August 2026, with employment types broken down into 77% Full Time, 20% Part Time, 2% Temporary, and 1% Contract. Highlights an 84% Physical, 3% Hybrid, and 13% Remote job distribution, with an average salary of $112,992 per year, or $54.3 per hour.

Principal ASIC Design Engineer

GreenWave Radios™

Irvine, CA

Full-time

Posted 23 days ago

Job description

InnoPhase Inc., DBA GreenWave Radios™, is at the forefront of innovation in Open RAN digital radios. Our cutting-edge solutions, powered by the Hermes64 RF SoC, are designed to enhance network energy efficiency while dramatically reducing operational expenses, with purpose-built silicon that is the heart of ORAN-based active antenna arrays.

Headquartered in San Diego, California, GreenWave Radios™ has established itself as a pioneer in delivering power-efficient digital-to-RF solutions. The company is supported by a talented team of over 100 engineers spread across four global R&D facilities. With an extensive portfolio of more than 120 global patents, GreenWave Radios™ continues to push the boundaries of radio technology and innovation.

To learn more about GreenWave Radios™ and hear what our employees have to say, visit the GreenWave™ certification profile at GreatPlacetoWork.com or explore our Home - GreenWave Radios website.

About the Role

We're looking for an experienced Principal Engineer/Manager to lead a small, high-impact team building next-generation cellular infrastructure radio Front Haul Gateway (FHGW) solutions in both FPGA and ASIC. You'll own everything from architecture through production—defining features, authoring device specifications, and driving the design flow for high-performance programmable logic with embedded Linux-based wireless communications software. This is a senior technical leadership and management role with direct influence on our market-leading cellular infrastructure products, working hands-on alongside experts across design, verification, firmware, and system engineering.

What You'll Do
  • Lead and mentor a small team of FPGA/ASIC design engineers, including resource planning, project scheduling, and technical mentoring/oversight
  • Own solution architecture end-to-end—taking marketing requirements and translating to product specifications through production-quality programmable logic design, verification and hardware validation
  • Drive architecture / micro-architecture definition, CPU/bus/memory subsystem design, IP integration, and physical implementation for complex SoC designs
  • Collaborate with system engineering on Radio product specifications, ensuring alignment across the company
  • Partner with IP, design verification, firmware, software, and production teams to close design issues and meet program milestones
  • Refine development methodologies and enforce design quality standards across the team, including simulation, linting, clock-domain crossing checks, and formal verification
  • Collaborate with embedded Linux-based wireless communications software team that complements the FPGA/ASIC logic layer
What You Bring
  • 20+ years of experience in FPGA and SoC development and mass production, including a proven track record in a technical leadership and management role
  • MS or PhD in Electrical Engineering or equivalent
  • Deep expertise in Verilog and SystemVerilog, and front-end tooling (simulation, linting, CDC, formal verification)
  • Hands-on experience with packet processing designs including buffering, routing, transposing, combining, framing/de-framing packet based formats (e.g. Ethernet, O-RAN/eCPRI, etc)
  • Hands-on experience with AMBA AXI/AHB/APB bus protocol specification and implementation
  • Proven ability to define constraints, run synthesis and static timing analysis, and own a complete front-to-back AMD (Xilinx Vivado) FPGA implementation flow
  • Working knowledge of DFT/DFM, SCAN ATPG, BIST, and fault coverage analysis
  • Proficiency in SystemVerilog and other advanced design verification methodologies
  • Comfort with scripting and programming languages including C/C++, Perl, Tcl, and Python
  • Strong communication and presentation skills; ability to drive results under aggressive schedules across cross-functional teams
Nice to Have
  • Experience developing cellular infrastructure radio products, particularly 10/25Gbps Ethernet eCPRI connectivity to the DU and interface to RF ASICs.
  • Familiarity with O-RAN FS7.2x specifications or eCPRI/CPRI front haul protocols
  • Understanding of Array based radios including AAU and mMIMO
  • Exposure to AI-assisted EDA tools for synthesis, timing analysis, or verification (e.g., AI-driven placement/routing assistants, ML-based timing closure prediction, AI-guided power analysis)
  • Experience using Claude Code or similar AI coding assistants to accelerate design scripting, documentation, or code review — familiarity with agentic AI tools for engineering workflows is a genuine differentiator
  • Familiarity with LLM-assisted RTL or HDL generation tools (e.g., Copilot for hardware, or general-purpose LLMs prompted for Verilog/SystemVerilog generation and review)
  • Comfort using AI tools for verification productivity — assertion generation, coverage analysis, or ML-based bug prediction to speed up simulation closure
  • Experience applying AI to technical documentation workflows — LLM-assisted datasheet parsing, specification drafting, or design review summarization
  • General comfort adopting AI-augmented workflows to boost design productivity
Compensation and Benefits

At InnoPhase, dba GreenWave Radios, our total rewards package includes both a competitive base salary and pre-IPO stock options. The anticipated base salary range for this position is $190,000 to $225,000 annually. Actual compensation will be determined based on several factors, including market conditions, interview performance, skills, qualifications, experience, education, and geographic location. In addition to base pay, employees are eligible for a comprehensive benefits package. For detailed information on our benefits programs, please visit our website.