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Asic Design Manager Jobs in California (NOW HIRING)

ASIC Engineer

San Jose, CA ยท On-site

$194K/yr

Drive design reviews, documentation, verification support, and cross-functional technical alignment ... management Qualifications: * BSEE required; MSEE or advanced degree preferred * Senior-level ...

ASIC/RTL Design Engineer 2

San Jose, CA ยท On-site

$60 - $62/hr

Hands-on experience in industry ASIC design flow including RTL coding, debugging/verification, and ... Good organizational, time management, and multitasking skills. * Strong initiative and discipline ...

Showing results 41-60

Asic Design Manager information

See California salary details

$41.5K

$113K

$198.9K

How much do asic design manager jobs pay per year?

As of Aug 8, 2026, the average yearly pay for asic design manager in California is $112,992.00, according to ZipRecruiter salary data. Most workers in this role earn between $82,400.00 and $142,100.00 per year, depending on experience, location, and employer.

Is ASIC design in demand?

ASIC design is in high demand due to the growth of industries such as consumer electronics, telecommunications, and automotive technology. Skilled ASIC design managers with expertise in hardware description languages and verification tools are sought after to develop custom integrated circuits for various applications.

What is the difference between Asic Design Manager vs Asic Design Engineer?

AspectAsic Design ManagerAsic Design Engineer
ResponsibilitiesOversees ASIC design projects, manages teams, and coordinates with stakeholdersPerforms ASIC design, coding, simulation, and verification tasks
Required SkillsLeadership, project management, ASIC design knowledgeHardware description languages, circuit design, verification skills
ExperienceTypically 8+ years in ASIC design, with leadership experienceUsually 2-5 years in ASIC design roles
Work EnvironmentDesign teams, project planning, cross-functional collaborationDesign labs, simulation environments, coding and testing

The main difference between an Asic Design Manager and an Asic Design Engineer lies in their roles. The manager oversees projects and teams, focusing on leadership and coordination, while the engineer concentrates on technical ASIC design and implementation. Both roles require ASIC design expertise, but the manager's role is more strategic and supervisory.

What are the key skills and qualifications needed to thrive as an ASIC Design Manager?

To thrive as an ASIC Design Manager, you need expertise in digital and analog ASIC design, project management experience, and typically a degree in electrical engineering or a related field. Familiarity with industry-standard EDA tools (such as Cadence or Synopsys), verification methodologies, and knowledge of relevant design flows is crucial. Strong leadership, communication, and problem-solving skills help manage teams and coordinate with cross-functional stakeholders. These competencies ensure high-quality chip designs are delivered on time and meet performance and cost targets, which is vital for organizational success.

Is ASIC design difficult?

ASIC design is a complex process that requires strong knowledge of digital logic, hardware description languages like VHDL or Verilog, and familiarity with electronic design automation tools. It involves multiple stages such as architecture, verification, and testing, making it challenging but manageable with proper training and experience.

What are some common challenges faced by an ASIC Design Manager in leading multidisciplinary teams?

ASIC Design Managers often navigate the complexities of coordinating multidisciplinary teams, including digital, analog, verification, and physical design engineers. One common challenge is ensuring clear communication across these specialties to maintain alignment on project goals, timelines, and technical requirements. Additionally, managing shifting priorities, resolving technical bottlenecks, and balancing resource allocation are frequent hurdles. Successful managers foster collaboration, set clear expectations, and leverage structured project management practices to keep teams productive and motivated.

What does an ASIC Design Manager do?

An ASIC Design Manager oversees the design and development of Application Specific Integrated Circuits (ASICs), managing a team of engineers through the entire chip design process. They coordinate project timelines, ensure technical specifications are met, and facilitate communication between design, verification, and manufacturing teams. Their role also involves resource planning, risk management, and ensuring that the final product meets performance, cost, and quality targets.
What are the most commonly searched types of Asic Design jobs in California? The most popular types of Asic Design jobs in California are:
What are popular job titles related to Asic Design Manager jobs in California? For Asic Design Manager jobs in California, the most frequently searched job titles are:
What job categories do people searching Asic Design Manager jobs in California look for? The top searched job categories for Asic Design Manager jobs in California are:
What cities in California are hiring for Asic Design Manager jobs? Cities in California with the most Asic Design Manager job openings:
Infographic showing various Asic Design Manager job openings in California as of August 2026, with employment types broken down into 77% Full Time, 20% Part Time, 2% Temporary, and 1% Contract. Highlights an 84% Physical, 3% Hybrid, and 13% Remote job distribution, with an average salary of $112,992 per year, or $54.3 per hour.

Principal ASIC Design Engineer

Hewlett Packard Enterprise Development LP

Sunnyvale, CA โ€ข Hybrid

Full-time

Re-posted 25 days ago


Job description

Principal ASIC Design EngineerThis role has been designed as 'Hybrid' with an expectation that you will work on average 2 days per week from an HPE office.

Who We Are:

Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today's complex world.Our culture thrives onfinding new and better ways to accelerate what's next.We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs.We make bold moves, together, and are a force for good. If you are looking to stretch and grow your career our culture will embrace you.Open up opportunities with HPE.

Job Description:

Job Family Definition:

Designs, analyzes, develops, modifies and evaluates VLSI components and hardware systems. Determines architecture and logic design, design verification through software developed for component and system simulation and builds physical implementations through development of multidimensional designs involving the layout of complex integrated circuits. Analyzes designs to establish operating data, conducts experimental tests and evaluates results to enable prototype and production VLSI solutions. May direct support personnel in the preparation of detailed design, design testing and prototype fabrication.

Management Level Definition:

Contributions have visible technical impact on a product or major subcomponent. Applies in-depth professional knowledge and innovative ideas to solve complex problems. Visible contributions improve time-to-market, achieve cost reductions, or satisfy current and future unmet customer needs. Recognized internal authority on key technology area applying innovative principles and ideas. Provides technical leadership for significant project/program work. Leads or participates in cross-functional initiatives and contributes to mentorship and knowledge sharing across the organization.

Responsibilities:

  • Architect complex modules and subsystems used in high performance networking chips.

  • Write detailedfunctionalas well as the micro-architecture specification for yourmodule withthatmeet the power/area/performance targets.

  • Implement the design using Verilog or System Verilog

  • Write functional coverage/SVA to help verification catch corner case bugs.

  • Make sure your module meets the power targets by usingstate-of-the-artpower reduction techniques during architecture and implementation phases.

  • Work with Physical design team for timing closure. Fix timing in RTL to meet the frequency target.

  • Collaborate with the Verification team to make sure your block is fullyvalidated.

  • Show leadership and provide guidance to new college-grad/juniorengineers and interns.

Recommended skills

  • Bachelor's degree in Electrical Engineeringrequired (Master'sstronglydesired) with 15+ years of relevant experience.

  • Strong analytical/ problem solving skills.

  • Demonstrated skills inleading andimplementing high performancesubsystemsfrom specification to final netlist.

  • Knowledge of Computer Architecture/networking protocols through prior work isstronglydesired.

  • Strong coding skills in Verilog/System Verilog throughpreviouswork experience are necessary.

  • Knowledge of synthesis/lint and other tools used in typical ASIC developmentprocessis highly desired.

  • Excellent written and verbal communications skillsisnecessary.

  • Knowledge of Perl/Python is strongly desired.

What We Can Offer You:

Health & Wellbeing

We strive to provide our team members and their loved ones with a comprehensive suite of benefits that supports their physical, financial and emotional wellbeing.

Personal & Professional Development

We also invest in your career because the better you are, the better we all are. We have specific programs catered to helping you reach any career goals you have - whether you want to become a knowledge expert in your field or apply your skills to another division.

Unconditional Inclusion

We are unconditionally inclusive in the way we work and celebrate individual uniqueness. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good.

Let's Stay Connected:

Follow @HPECareers on Instagram to see the latest on people, culture and tech at HPE.

#unitedstates

Job:

Engineering

Job Level:

TCP_05"The expected salary/wage range for this position is provided below. Actual offer may vary from this range based upon geographic location, work experience, education/training, and/or skill level.
- United States of America: Annual Salary USD 174,000 - 352,500 in California
The listed salary range reflects base salary. Variable incentives may also be offered."

Information about employee benefits offered in the US can be found at https://myhperewards.com/main/new-hire-enrollment.html

HPE is an Equal Employment Opportunity/ Veterans/Disabled/LGBT employer. We do not discriminate on the basis of race, gender, or any other protected category, and all decisions we make are made on the basis of qualifications, merit, and business need. Our goal is to be one global team that is representative of our customers, in an inclusive environment where we can continue to innovate and grow together. Please click here: Equal Employment Opportunity.

Hewlett Packard Enterprise is EEO Protected Veteran/ Individual with Disabilities.

HPE will comply with all applicable laws related to employer use of arrest and conviction records, including laws requiring employers to consider for employment qualified applicants with criminal histories.

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Please note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendorswill never charge any candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process.The credentials of any hiring agency that claims to be working with HPE for recruitment of talent should be verified by candidates and candidates shall be solely responsible to conduct such verification. Any candidate/individual who relies on the erroneous representations made by fraudulent employment agencies does so at their own risk, and HPE disclaims liability for any damages or claims that may result from any such communication.