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Remote Asic Physical Design Engineer Jobs in California

Meta

ASIC Engineer, Power

Sunnyvale, CA · On-site +1

$146K/yr

Collaborate with RTL design, physical design, and verification teams to identify and resolve power hotspots and inefficiencies across custom ASIC designs * Build and optimize EDA infrastructure ...

Tensordyne

Principal ASIC Architect

Sunnyvale, CA · On-site +1

Headquartered in Sunnyvale, CA, and Munich, Germany, with remote team members across North America ... design engineers, ASIC design verification teams, SOC physical design teams, interdisciplinary ...

AttoTude

MMIC Design Engineer

Menlo Park, CA · On-site +1

$160K - $250K/yr

We are seeking a highly experienced THz IC Design Engineer to join our growing team. In this role ... Understanding tradeoff at the device level for high performance ASIC implementation * Ability to ...

AttoTude

MMIC Design Engineer

Menlo Park, CA · On-site +1

We are seeking a highly experienced THz IC Design Engineer to join our growing team. In this role ... Understanding tradeoff at the device level for high performance ASIC implementation * Ability to ...

Meta

ASIC Engineer, Design Verification

Sunnyvale, CA · On-site +1

$146K/yr

Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design Verification to build IP and System On Chip (SoC) for ...

Meta

ASIC Engineer, Design Verification

Sunnyvale, CA · On-site +1

$114K/yr

Meta is hiring an ASIC Design Verification Engineer within the Infrastructure Silicon organization. We are looking for individuals with experience in Design Verification to build IP and System on ...

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Remote Asic Physical Design Engineer information

What does a remote ASIC physical design engineer do?

A Remote ASIC Physical Design Engineer is responsible for transforming circuit designs into physical layouts that can be manufactured as integrated circuits (ICs), specifically Application-Specific Integrated Circuits (ASICs). Their role includes tasks such as floorplanning, placement, routing, timing analysis, and verifying that the physical design meets performance and power specifications. Working remotely, they collaborate with design and verification teams using specialized EDA (Electronic Design Automation) tools to optimize chip layouts for manufacturability and efficiency. Effective communication and expertise in physical design processes are essential for success in this role.

What are the key skills and qualifications needed to thrive as a remote ASIC physical design engineer?

To thrive as a Remote ASIC Physical Design Engineer, you need a strong background in digital logic design, ASIC implementation, and a relevant engineering degree. Proficiency with industry-standard EDA tools such as Synopsys, Cadence, or Mentor Graphics, as well as scripting languages like TCL and Python, is typically required. Excellent problem-solving, communication, and time management skills are vital for effective remote collaboration and project delivery. These skills and qualifications ensure high-quality chip designs, efficient workflow, and seamless teamwork in a distributed environment.

What are some common challenges faced by a remote ASIC physical design engineer, and how can they be addressed?

Remote ASIC Physical Design Engineers often encounter challenges related to communication and collaboration, especially when coordinating with cross-functional teams such as verification, synthesis, and EDA tool support. Time zone differences and limited face-to-face interaction can make it harder to quickly resolve design issues or clarify specifications. To overcome these challenges, engineers should leverage collaborative tools, maintain clear documentation, and proactively schedule regular check-ins with team members. Building strong virtual communication habits helps ensure smooth project execution and timely delivery of design milestones.

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Remote Asic Physical Design Engineer jobs near you
Infographic showing various Remote Asic Physical Design Engineer job openings in California as of August 2026, with employment types broken down into 85% Full Time, 5% Part Time, and 10% Contract. Highlights an 100% Remote job distribution.

Principal Physical Design Engineer

Celero Communications

San Jose, CA • On-site, Remote

$200K - $300K/yr

Full-time

This job post has expired today. Applications are no longer accepted.

Job description

Principal Physical Design Engineer
Core Responsibilities
•RTL-to-GDSII Execution: Own physical implementation of System-on-Chips (SoCs) or complex digital blocks.
•Design Optimization: Manage floor-planning, bump planning, power grid design, and clock tree synthesis (CTS) to optimize chip performance.
•Design Convergence: Resolve timing, congestions, EM/IR issues together with Frontend Designers
•Signoff & Verification: Run Static Timing Analysis (STA) and physical verification. Fix Design Rule Checking (DRC) and Layout Versus Schematic (LVS) violations.
•Methodology Development: Drive automation and improve flow robustness using scripting languages like Tcl, Python, or Perl.
•Cross-Functional Leadership: Partner with architects, logic designers, and analog design team for tapeout readiness.
Key Qualifications
•Experience: 7+ to 15+ years of relevant ASIC physical design experience (depending on degree level).
•Process Knowledge: Deep tapeout experience in advanced technology nodes (e.g., 7nm, 5nm, 3nm).
•Tool Mastery: Advanced proficiency with industry-standard EDA tools from vendors like Cadence (e.g., Innovus, , Tempus, Voltus, Pegasus, Calibre).
•Technical Concepts: Expertise in physically aware synthesis, power domain analysis, and Electromigration/IR-drop (EM/IR) cleanup.
Annual Base Salary Range: $200,000 to $300,000 (The final offer will be determined based on job-related skills, experience, qualifications, and location.)
Javier Leon
Talent Acquisition
619-227-3193 cell/text
javier.leon@celero.inc
www.celero.inc

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