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Remote Asic Physical Design Engineer Jobs in California

As an EDS Design Engineer, you will be at the forefront of defining the "nervous system" for our ... While your primary focus is the robust physical design and routing of the harness, you will work ...

Substation Engineer

San Diego, CA · On-site +1

$95K - $140K/yr

Ability to work independently in a remote environment while collaborating effectively with engineering and project teams. Preferred Experience * Substation physical design. * Protection and control ...

New

Collaborate closely with the Full Chip owner on the Physical Design team to incorporate necessary ... Remote Perks We work remotely Monday & Friday, supported by home-tech setup, and remote wifi ...

Substation Engineer

San Diego, CA · On-site +1

$95K - $140K/yr

Ability to work independently in a remote environment while collaborating effectively with engineering and project teams. Preferred Experience * Substation physical design. * Protection and control ...

New

Substation Engineer

San Diego, CA · On-site +1

$95K - $140K/yr

Ability to work independently in a remote environment while collaborating effectively with engineering and project teams. Preferred Experience * Substation physical design. * Protection and control ...

New

Staff Product Design Engineer

San Francisco, CA · On-site +1

$152K - $182K/yr

... or physical disability, national origin, protected family care or medical leave status, race ... We've been alerted to scammers posing as OURA recruiters, especially for remote roles. Please note:

Staff Product Design Engineer

San Francisco, CA · On-site +1

$152K - $182K/yr

We've been alerted to scammers posing as ŌURA recruiters, especially for remote roles. Please note ... or physical disability, national origin, protected family care or medical leave status, race ...

Staff RFIC Design Engineer

San Jose, CA · On-site +1

$144K - $187K/yr

Experience supporting remote engineering teams. * Be able to work independently, communicate well ... on physical location) Posted salary ranges are made in good faith. Qorvo reserves the right to ...

Posted today

Senior EDS Design Engineer

Palo Alto, CA · On-site

$138K - $232K/yr

As an EDS Design Engineer, you will be at the forefront of defining the "nervous system" for our ... While your primary focus is the robust physical design and routing of the harness, you will work ...

Cad Engineer

Arvin, CA · On-site +1

$100K - $120K/yr

Job Title: CAD Engineer We are seeking an experienced CAD Engineer with a robust background in BIM ... Work Environment This is a remote position with occasional visits to Tejon Ranch. You will work in ...

Design Engineer, Mobile

San Francisco, CA · On-site +1

$220K - $350K/yr

Without design engineers as influential voices in the company, none of this would be possible. And ... We fly remote teammates to SF for three to four days a month. Visa sponsorship. We sponsor visas:

Showing results 41-60

Remote Asic Physical Design Engineer information

What does a remote ASIC physical design engineer do?

A Remote ASIC Physical Design Engineer is responsible for transforming circuit designs into physical layouts that can be manufactured as integrated circuits (ICs), specifically Application-Specific Integrated Circuits (ASICs). Their role includes tasks such as floorplanning, placement, routing, timing analysis, and verifying that the physical design meets performance and power specifications. Working remotely, they collaborate with design and verification teams using specialized EDA (Electronic Design Automation) tools to optimize chip layouts for manufacturability and efficiency. Effective communication and expertise in physical design processes are essential for success in this role.

What are the key skills and qualifications needed to thrive as a remote ASIC physical design engineer?

To thrive as a Remote ASIC Physical Design Engineer, you need a strong background in digital logic design, ASIC implementation, and a relevant engineering degree. Proficiency with industry-standard EDA tools such as Synopsys, Cadence, or Mentor Graphics, as well as scripting languages like TCL and Python, is typically required. Excellent problem-solving, communication, and time management skills are vital for effective remote collaboration and project delivery. These skills and qualifications ensure high-quality chip designs, efficient workflow, and seamless teamwork in a distributed environment.

What are some common challenges faced by a remote ASIC physical design engineer, and how can they be addressed?

Remote ASIC Physical Design Engineers often encounter challenges related to communication and collaboration, especially when coordinating with cross-functional teams such as verification, synthesis, and EDA tool support. Time zone differences and limited face-to-face interaction can make it harder to quickly resolve design issues or clarify specifications. To overcome these challenges, engineers should leverage collaborative tools, maintain clear documentation, and proactively schedule regular check-ins with team members. Building strong virtual communication habits helps ensure smooth project execution and timely delivery of design milestones.

What job categories do people searching Remote Asic Physical Design Engineer jobs in California look for?

The top searched job categories for Remote Asic Physical Design Engineer jobs in California are:

What cities in California are hiring for Remote Asic Physical Design Engineer jobs?

Cities in California with the most Remote Asic Physical Design Engineer job openings:

Infographic showing various Remote Asic Physical Design Engineer job openings in California as of August 2026, with employment types broken down into 85% Full Time, 5% Part Time, and 10% Contract. Highlights an 100% Remote job distribution.

Senior/Principal Physical Verification Engineer

Celero Communications, Inc.

San Jose, CA • On-site, Remote

$150K - $250K/yr

Full-time

Posted 13 days ago


Job description

Senior to Principal Full-Chip Physical Verification Engineer roles
Locations: San Jose, CA (preferred) or Irvine, CA (HQ) or remote
Key Responsibilities
Team & Project Leadership
• Lead full chip Physical Verification effort
• Own execution plans, schedules for full-chip
• Drive accountability for quality, milestones, and tapeout readiness.
• Conduct full chip and blocks PV checks
Physical Verification Ownership
• Ownership of full chip verification
• Work with internal analog team to ensure clean IP delivery
• Responsible for running and analyzing DRC/ERC/LUP/PERC results
• Experience with using either ICV or Calibre verification tools
• Understanding advance TSMC DRC rules
Cross-Functional Collaboration
• Partner with analog, block, chip top owners to ensure clean floorplan
• Provide early guidance on corner case requirements
• Influence floorplan constraints, hierarchy, and implementation strategy
• Participate in tapeout readiness reviews
Required Qualifications
• Bachelor’s or Master’s degree in Electrical Engineering or related field.
• 7+ years of experience with full-chip verifications
Proven hands-on experience with:
• Physical Verification tool (ICV/Calibre)
• Able to assemble a flow to support block/chip level PV
Strong expertise in:
• Floorplanning to avoid DRC/LVS issues
• Provide guidance to analog IP team to allow for clean integration
Preferred Qualifications
• Experience in advanced technology nodes (7nm, 5nm, 3nm)
• Automation skills using Tcl, Python, or shell scripting
Annual Base Salary Range: $150,000 - $250,000 (The final offer will be determined based on job-related skills, experience, qualifications, and location)